[Verilog quick start of Niuke network question brushing series] ~ priority encoder circuit ①

0. Preface

The previous ten questions are Verilog Basic grammar of , I think we must master , But in the second part, these questions of combinatorial logic are suddenly a little disgusting , So I chose to do this question , What kind of questions can I do ？

I will share the questions that involve important knowledge points .

0.1 Knowledge point

0.1.1 About case、casex、casez The difference between

Let's look at it first case、casex、casez Corresponding truth table

0.1.2 explain ：

1. stay case In the sentence , The comparison between sensitive expressions and values is a congruent comparison , Only when everyone is the same will it be considered a match .

2. stay casez In the sentence , If the value of some bits of the branch expression is high impedance z, Then the comparison of these bits will be ignored , Don't consider , And only focus on the comparison results of other bits .

3. stay casex In the sentence , Then this processing method is further extended to x To deal with , That is, if the value of some bits of one side of the comparison is z or x, Then the comparison of these bits will not be considered .

0.1.3 matters needing attention

1. Commonly used is casez sentence , Better use less casex
2. case/casez/casex In fact, they are all integrable
3. In the circuit , It can be used ？ To represent irrelevant values z
4. case Description of , Matching is done from top to bottom

1. VL13 Priority encoder circuit ①

Write the address , Portal

1.1 Title Description

The following table is the truth table of a priority encoder .
① Please use Verilog Implement this priority encoder

1.1.1 Signal schematic diagram

nothing

1.1.2 Waveform diagram

nothing

1.1.3 Input description

input [8:0] I_n

1.1.4 Output description

output reg [3:0] Y_n

1.2 Their thinking

The truth table given by the title , Write out the corresponding input and output in turn （ Pay attention to high and low position ）.

1.3 Code implementation

`timescale 1ns/1ns

module encoder_0(
   input      [8:0]         I_n   ,
   
   output reg [3:0]         Y_n   
);

    always @(*)begin
       casez(I_n)
          9'b111111111 : Y_n = 4'b1111;
          9'b0zzzzzzzz : Y_n = 4'b0110;
          9'b10zzzzzzz : Y_n = 4'b0111;
          9'b110zzzzzz : Y_n = 4'b1000;
          9'b1110zzzzz : Y_n = 4'b1001;
          9'b11110zzzz : Y_n = 4'b1010;
          9'b111110zzz : Y_n = 4'b1011;
          9'b1111110zz : Y_n = 4'b1100;
          9'b11111110z : Y_n = 4'b1101;
          9'b111111110 : Y_n = 4'b1110;
          default      : Y_n = 4'b1111;
       endcase    
    end 
endmodule

1.4 The test file

To be changed ...

1.5 Simulation waveform

To be changed ...

Statement

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