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建立时间和保持时间的模型分析
2022-07-06 00:16:00 【傻童:CPU】
建立时间和保持时间的模型分析
起点是源触发器D1的采样时刻,终点是目的触发器D2的采样时刻,假设起点已经满足了建立时间和保持时间要求,现在分析终点采样时刻是否同样满足要求。
其中
- Tco:数据正确采样后从D端到达Q端的延时,触发器固有属性,不可改变。
- TDelay:D1输出端到D2输入端的组合逻辑延时和布线延时。
- Tsu:触发器的建立时间,触发器的固有属性,不可改变。
- Th:触发器的保持时间,触发器的固有属性,不可改变。
- Tclk:时钟周期。
- t1:假设源时钟为clka,clka到达D1的延时。
- t2:clka到达D2的延时。
触发器的行为:时钟沿到来时采样数据D,将采到的数据寄存下来,并输出到Q端,所有如果没有新的时钟沿到来,则Q端输出的一直是上次采样的数据,每来一个时钟沿,采样一次数据D。
假设clk传输没有延时:则每一个时钟上升沿都会同时到达D1和D2。时间起点,第一个时钟沿D1的采样时刻,时间终点,第二个时钟沿D2的采样时刻。物理起点,D1的输入端,物理终点,D2的输入端。
建立时间满足(关注数据头):第一个时钟沿到来时,数据 data 的头部从起点①开始传输,经过 Tco 到达②,在经过 TDelay
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