Verilog daily question (vl4 shift operation and multiplication)

Title Description ：     

It is known that d For one 8 digit , Please output this number in each clock cycle 1/3/7/8, And output a signal to inform the input at this time d It works （d The rising edge of the given signal indicates that the write is valid ）

Waveform diagram ：

Here I have two ways to solve problems ：

（1） Create variables to count , Output through a loop

（2） Use state machine to design

Because the way of state machine is more intuitive , Here we use the state machine to solve the problem directly （merely type , Related to both input and current state ）

Set up 5 States ： A standby state , Four cyclic States , The specific solution ideas are as follows

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
    parameter a=0,b=1,c=2,d1=3,e=4;
    reg [7:0] d0;
    reg [2:0] state,nstate;
    always @(posedge clk,negedge rst)
        begin
            if(!rst) begin state=a;out=0;input_grant = 0; end
            else begin
                state = nstate;
                d0 = (state==b)? d:d0;
                //state==b When the value is assigned , And only when the state returns b The next assignment will be made only when 
                input_grant = (state==b);
                out = (state==b)? d0 :(state==c)? 3*d0 :(state==d1)? 7*d0 :(state==e)?8*d0 :0;
                // You can't write directly here d, Because in a cycle ,d The change of the value of does not affect the calculated four values with clk Appear along the rising edge , Added a d0 To replace 
            end
        end
    always @(*)
        begin
            case(state)
                a: nstate = b; //a It's the initial state 
                b: nstate = c; // To state b The calculation starts at 
                c: nstate = d1;
                d1: nstate = e;
                e: nstate = b;
                default nstate=a;
            endcase
        end
//*************code***********//
endmodule

Finally, I looked at the answer and directly used one case Circular , It's easier .