Competition and adventure burr

Summary

Generally speaking , Take risks to eliminate competition , Increase filter capacitance and logic redundancy , Are not Verilog Design considerations .

Gray code counter is used for counting , Most of them are also used to reduce the power consumption by reducing the signal turnover rate under the high-speed clock .

The trigger is used to delay the asynchronous signal under the clock synchronization circuit , yes Verilog Methods often used in design .

besides , Take risks to eliminate competition ,Verilog There are still some problems to pay attention to when coding , See the next section .

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Verilog Writing norms

Pay more attention to the following points when programming , It can also avoid most of the problems of competition and adventure .

• • 1） When modeling sequential circuits , Non blocking assignment .
  • 2） When modeling combinatorial logic , Assignment with blocking .
  • 3） In the same always When building temporal and combinatorial logic models in blocks , Non blocking assignment .
  • 4） In the same always Do not use both blocking and non blocking assignments in blocks .
  • 5） Don't be in more than one always Assign a value to the same variable in the block .
  • 6） avoid latch produce .