interrupt and pendSV

1. Overview

The reader has already understood the detailed process of task switching through the task and task switching section. In fact, it is far from enough to realize the function of task switching.Because, the operation of PSP must be in privileged mode, and the user's program is working in thread mode.Therefore, if the user wants to realize the task switching function, he must find a way to make the CPU work in the privileged mode.I might need to know more to understand how embedding is an operating system implementation.

The following content is highly platform-dependent, but the principles are similar.The content mentioned here is explained based on the ARM Cortex-M processor.

2. Operating modes and privilege levels of the CPU

Generally, a CPU will have different operation modes and privilege levels to realize the distinction between the operating system level and the user level, and then further control the operation authority.We all know that each user of the Linux system has different operating permissions from the root user, and the application layer and the kernel layer also have different permissions for hardware operations.How does Linux implement permission control?I wonder if any readers have asked similar questions?In fact, the control of permissions is not only implemented at the software level, but also needs to be supported by hardware at a certain level.

We take the ARM Cortex-M family of processors as an example, which supports two processor operating modes and two privilege levels.

Two modes of operation:

• handler mode: interrupt and exception execution code is in this mode
• thread mode: other code is in this mode

The original intention of introducing the two modes is to distinguish the code of the ordinary application and the code of the exception service routine - including the code of the interrupt service routine.

Two privilege levels:

• Privilege Level
• User level

This can provide a protection mechanism for memory access, so that ordinary user program code cannot accidentally, even maliciously, perform critical operations.The processor supports two privilege levels, which is also a basic security model.