Pci/pcie related knowledge

PCI/e Configuration space

PCI/PCIe The configuration space of Configuration Space It's a relationship with Memory Space and IO Space juxtaposed independent space .PCI Configuration Space Yes 256 Bytes, about PCIe Configuration Space, Expand to 4096 Bytes,PCIe Is in PCI Agreements developed on the basis of , And on this basis, it is extended , Its extended form is through a method called Capability Register block to complete .

 

access

IO The way

CPU Two groups are provided I/O Registers are used to access the configuration space ：

• Configure the space control register CF8h-CFBh
• Configure the spatial data register CFCh-CFFh

The traditional way , Write IO port CFCh and CF8h. Only access PCI/PCIe Start of equipment 256 Bytes （PCI The configuration space of the device is only 256 Bytes ......）

// for PCI
address = BIT31 | ((Bus & 0xFF) << 16) | ((Dev & 0x1F) << 11) | ((Fun & 0x7) << 8) | (Reg & 0xfffffffc);//BIT31=0x80000000

// write cfg register
IoWrite8(0xcf8, address);
// read data register
data8  = IoRead8(0xcfc);
data16 = IoRead16(0xcfc);
data32 = IoRead32(0xcfc);

 Bit31 representative enable bit. Be sure to put it up , Otherwise it doesn't work .

MMIO The way

about MMIO The interview of , Just like accessing memory , It is called PCIEXBAR Start at the base address of , There's a lot of space , This PCIEXBAR The value of may vary depending on the platform , The approximate possible values are 0xB0000000、0xC0000000 etc. （ Feiteng uses 0xB0000000）.

#define pcie_addr(m, b, d, f, o)        (m + ((b & 0xff) << 20) + ((d & 0x1f) << 15) + ((f & 0x7) << 12) + (o & 0xfffffffc)
#define mmio_read8(addr)            (*(volatile uint8 *)addr)
#define mmio_write8(addr, data8)    *(volatile uint8 *)addr = data8
#define mmio_read16(addr)           (*(volatile uint16 *)addr)
#define mmio_write16(addr, data16)  *(volatile uint16 *)addr = data16
#define mmio_read32(addr)           (*(volatile uint32 *)addr)
#define mmio_write32(addr, data32)  *(volatile uint32 *)addr = data32

A pair of... Is reserved in the configuration register group PCI Readable information that describes in detail the basic characteristics of the equipment ,CPU After reading this information , You can for PCI The equipment settings meet the required configuration contents , So as to realize automatic configuration . This readable information includes ：

Vendor ID ： Equipment supplier number , from PCI SIG Distribution by international organizations .

Device ID ： Specific equipment number , Assigned by the equipment supplier .

Revision ID ： The specific version number of the device , Assigned by the equipment supplier .

Class Code ： The functional category number of the equipment .

Header Type ： instructions Header  From the address 10H To 3FH Content format of the region , It also indicates whether the device is a multi-function device .

scanning PCI When the equipment , We can go straight through Vendor ID And Device ID Is it 0xffff To determine whether the device exists , If it is , Then the device does not exist , But there is also a situation , Domestic production is not complete , When designing hardware , It is quite possible that this nonexistent value is not 0xffff, It could be 0 It doesn't exist ：

//
  // Create PCI address map in terms of Bus, Device and Func
  //
  Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);

  //
  // Read the Vendor ID register
  //
  Status = PciRootBridgeIo->Pci.Read (
                                  PciRootBridgeIo,
                                  EfiPciWidthUint32,
                                  Address,
                                  1,
                                  Pci
                                  );

  if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff && (Pci->Hdr).VendorId != 0) {
    //
    // Read the entire config header for the device
    //
    Status = PciRootBridgeIo->Pci.Read (
                                    PciRootBridgeIo,
                                    EfiPciWidthUint32,
                                    Address,
                                    sizeof (PCI_TYPE00) / sizeof (UINT32),
                                    Pci
                                    );

    return EFI_SUCCESS;
  }

This part of the code is PciEnumeratorSupport.c There is a definition in the document