[FPGA tutorial case 8] design and implementation of frequency divider based on Verilog

FPGA Tutorial directory

MATLAB Tutorial directory

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1. Software version

vivado2019.2

2. This algorithm has theoretical knowledge and Verilog Program

      In practice FPGA Development process , The clock of the system clk Often larger , The actual clock frequency required is low , Then you need to divide the frequency of the system clock , Get a low frequency clock signal . In this course , The clock frequency division will be realized through the counter . The implementation process of the counter can review the previous course .

【FPGA Tutorial cases 7】 be based on verilog Design and implementation of counter based on

here , On the basis of this counter , Add the following verilog Program ：

`timescale 1ns / 1ps
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// Create Date: 2022/07/02 22:35:42
// Design