USB (XV) 2022-04-14

                FX3 chip FPGA Development II read and write timing

1. Timing parameters

1.1 Timing parameters

AN65974 The operation is specified in the document GPIF II Interface timing parameters , The screenshot is as follows , Figure 1 shows the synchronous slave device reading sequence , Figure 2 shows the synchronous slave device write sequence , chart 3 It's synchronization ZLP Write cycle timing , chart 4 Is the specific parameter value . It should be noted , This is a Cyusb3014 Timing requirements of the chip , It has nothing to do with what the external controller is . In addition, pay attention to ,PCLK The signal is transmitted by the external controller to Cyusb3014 The clock of , Not its own . You can see , In addition to describing timing parameters, these diagrams , It also points out the sequence of read and write operations , This article will be analyzed as a separate section later .

chart 1 Synchronize the sequence read from the device