Start from the bottom structure to learn the customization and testing of FPGA --- Xilinx ROM IP

List of articles

Series catalog and portal

1、 What is? ROM？ 

2、ROM IP Customization of nuclear power

Get ready  

①、 first page  

②、 The second page

③、 The third page  

④、 Page four

3、ROM IP Example and simulation test of

3.1、 Exemplify a ROM IP nucleus

3.2、 The simulation test

4、 Summary and reference

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Series catalog and portal

       《 Start with the underlying structure FPGA》 Directory and portal

        Customizing one RAM IP Before nuclear , It is strongly recommended that you read ：

                 Start with the underlying structure FPGA----RAM IP Introduction to nuclear and key parameters

                 Start with the underlying structure FPGA----Xilinx RAM IP Customization and testing of

         In the above two articles , Have been to RAM IP The key factors of nuclear are explained in detail , Also on RAM IP We made a customization and test for the instantiation of .

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1、 What is? ROM？ 

         In this paper, we introduce a new method in FPGA Storage classes commonly used in development IP nucleus ——ROM How to use .

        ROM Read only memory （Read-Only Memory） For short , It is a solid-state semiconductor memory that can only read out the data stored in advance . Its characteristic is that once the data is stored, it can no longer be changed or deleted , And the data will not disappear because the power is turned off . And in fact FPGA Pass through IP Nucleated ROM or RAM All the calls are FPGA Inside BRAM resources , Power down content will be lost （ It's also easy to explain ,FPGA There is no power down nonvolatile memory unit inside the chip ）.

         use IP Nucleated ROM The module just adds data files in advance （.coe Format ）, stay FPGA At run time, data files are sent to ROM Module initialization , So that ROM The module is like a “ real ” Power down nonvolatile memory ; That's why ,ROM The contents of the module must be written in the data file in advance , Cannot modify... In a circuit . 

        Simply speak ,RAM Is a writable 、 Readable IP nucleus ; and ROM Just a readable but not writable IP nucleus . So you can put ROM As one is “ Youth version ” Of RAM, It only has RAM Read function of . in fact , stay xilinx Of FPGA In development ,RAM And ROM All of them are used BRAM Resource realization （ customized IP It's the same ）, But the external interface encapsulation is different .

        stay RAM IP chapter , We know RAM There are three forms of ：

• Single port RAM(Single-port RAM)
• Simple double mouth RAM(Simple Dual-port RAM, Also called pseudo dual port RAM)
• What a double mouth RAM(True Dual-port RAM)

        that ROM There are several forms of composition ？

         It's not hard to infer , Single port ROM It must be possible , That is, one port to read . So double port ROM Will there be two ？ Can't , because ROM The read-only but not write feature is doomed to have only one kind of double port ROM, That is, both ports are readable ROM. as follows ：

• Single port ROM（Single-Port Rom）
• Dual port ROM（Dual-Port ROM）

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（1） Single port ROM： Write operation cannot be realized , Only one port can be used for reading

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（2） Dual port ROM： Write operation cannot be realized , Two ports can be used for reading , The bit width of the read data of the two ports can be different , But it must be an integer multiple

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2、ROM IP Customization of nuclear power

        ROM IP Customization and RAM IP The customization process of the core is very similar , But there are fewer parameters to focus on , So the implementation is simpler . Next, we will show how to customize a bit width 4bit, depth 16 Single port ROM The process of .

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Get ready  

1. Create a new one ROM After the project, click the arrow IP Catalog
2. It will appear after clicking IP Catalog page , stay IP Search in the search box of the kernel block
3. According to the screening sequence , Double click the arrow RAM & ROM nucleus “Block Memory Generator”, After double clicking, the configuration interface will appear

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①、 first page  

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②、 The second page

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③、 The third page  

        About the initial file loaded （.coe file ）, It can be written in the following format , Then click on Browse selection ：

        You can also click ,Edit, Then create a new one .coe After the document , Write your own content （ It should be noted that , Do not use ; To the end ）：

        Yes, of course , What is loaded above is some relatively simple , Regular data . If the data you want to load is complex , It is recommended to use MATLAB Or other scripting software to generate , And save it as coe File reload . 

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④、 Page four

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3、ROM IP Example and simulation test of

3.1、 Exemplify a ROM IP nucleus

        Follow the above steps to generate IP after , Copy IP nucleus The self-contained instantiation template .

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         And then in our RTL In the code , Instantiate the ROM.RTL No other functions , Only instantiate ROM that will do .

module rom_test(
	input 			clk,		// Input clock 
	input			en,			// Enable signal 
	input	[3:0]	addr,		// Address 			
	output	[3:0]	data_out	// Output data 
);
 
// Exemplification ROM IP nucleus 
rom_w4_d16 rom_w4_d16_inst (
  .clka		(clk),   
  .ena		(en),    
  .addra	(addr), 
  .douta	(data_out)  
);
	
endmodule

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3.2、 The simulation test

         Write a testbench, Yes ROM IP Test it .

         Test behavior ： Write initialization file before (.coe) I already said , The contents loaded are 0、1、2······F. So after stabilization from the address 0-15 Reading data , Observe whether the read data is consistent with the initialization content .

`timescale 1ns / 1ns

module tb_rom_test();

reg 			clk;		
reg				en;			
reg		[3:0]	addr;			
wire	[3:0]	data_out;	

initial begin
	clk = 0;
	en = 0;
	addr = 0;
	
	#110	
	en = 1;					// Start reading data 
	repeat(18) begin		// From address 0-15 Reading data （ Plus the delay 3）
		#10	addr = addr + 1;		
	end
	en = 0;					// Stop reading data 	
	
	#20 $finish;			// End the simulation 	
end

always #5 clk = ~clk;		// Generate clock , cycle 10ns

// Instantiate the tested module rom_test
rom_test	rom_test_inst(
	.clk		(clk		),		
	.en			(en			),		
	.addr		(addr		),		
	.data_out	(data_out	)		
);

endmodule

        Use vivado Built in simulation tools simulator Run the simulation , The simulation results are as follows ：

        stay 3 After a delay of clock cycles , The data read out are 0、1、2······、F, In line with the expected results . 

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4、 Summary and reference

• You can see ROM IP The customization of is very simple , It's basically a “ Youth version ” Of RAM IP.
• It's not easy to create , If this article helps you , Please give me more praise 、 Reviews and collections . Your support is the biggest driving force for me to continuously update ！

Reference material 1：Block Memory Generator v8.4

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• Blog home page ：wuzhikai.blog.csdn.net
• This paper is written by   Lonely single blade   original , First appeared in CSDN platform
• Do you have any questions , You can communicate with me in the comment area ！
• It's not easy to create , Your support is the biggest driving force for me to continuously update ！ If this article helps you , Please give me more praise 、 Reviews and collections ！

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