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VHDL实现单周期CPU设计
2022-07-06 20:15:00 【QQ_778132974】
VHDL实现单周期CPU设计
在quartus下实现,顶层是原理图模式,语言使用VHDL,实现单周期CPU的功能,包括ALU,RAM,ROM,MUX,regfile等模块,下面有工程截图及仿真截图。
仿真截图:
ALU模块代码:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU_lrt is
port(a,b:in std_logic_vector(15 downto 0);
func:in std_logic_vector(3 downto 0);
c_lrt:out std_logic_vector(15 downto 0));
end ALU_lrt;
architecture behave of ALU_lrt is
begin
process (a,b,func)
begin
case func is
when “0000”=>c_lrt<=a and b;–and
when “0001”=>c_lrt<=a or b;–or
when “0010”=>c_lrt<=a xor b;–xor
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