[VHDL parallel statement execution]

General detection clock rising edge
Method 1 ：rising_edge Is a very strict rising edge , Must be from 0 To 1 ,
Method 2 ：(clk’event and clk=‘1’) It can be downloaded from X To 1
Both ways are well understood
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problem

Because of the recent contact FPGA, Study VHDL Language , Encountered a problem that beginners may encounter

			clk10khz_d1 <= clk10khz;   
            clk10khz_d2 <= clk10khz_d1;
            if key_cs='1' and clk10khz_d1='1' and clk10khz_d2='0' then   --( Judge the rising edge ）
                .......
            end if;

See here ,clk10khz The value of clk10khz_d1 , clk10khz_d1 The value of clk10khz_d2,
thus clk10khz ,clk10khz_b1 ,clk10khz_b2 It shouldn't be the same ？ Is it wrong ？
Later, I saw a lot of code to detect the rising edge , It's all like this , There's no explanation .

In fact, that is Nonblocking assignment and Block assignment The difference between , Senior VHDL Players will feel that this problem is too basic .

What is non blocking assignment ？

The non blocking assignment operator uses the less than or equal sign ( namely <=) Express .
For calculating the non blocking assignment character at the beginning of the assignment operation time RHS expression , Update at the end of the assignment operation time LHS. When calculating non blocking assignment RHS Expressions and updates LHS period , Other statements , Including other non blocking assignment statements can be calculated at the same time RHS Expressions and updates LHS. Nonblocking assignment allows other statements to operate at the same time .

The non blocking assignment is determined by the clock beat , When the clock rises , Execute the assignment statement , And then begin-end All assignment statements between are assigned to the left of the assignment statement at the same time , Be careful ： yes begin—end All statements between , Do it together , And a clock executes only once .

The results of two different assignment methods are different , Nonblocking assignment b<=a;c<=b; Two statements are executed at the same time , And block assignment b=a;c=b; Two statements are executed first b=a After execution c=b.

Why can we detect the rising edge ？

Know what is non blocking assignment , Then it is easy to understand the method of detecting the rising edge

			clk10khz_d1 <= clk10khz;   
            clk10khz_d2 <= clk10khz_d1;

Execute two sentences together , hypothesis clk10khz Status as …01… ( On the rising edge ）
At low levels clk10khz_d1 , clk10khz_d2 Are endowed with 0 ,
Along the rising edge , When executing two sentences at the same time clk10khz_d2 still Before being clk10khz_d1 The stored value is assigned to 0;
here clk10khz Rise to 1 , clk10khz_d1 To be an assignment 1.

Thus through clk10khz_d1='1' and clk10khz_d2='0 The rising edge of the detection signal .

That is to say, the order of two assignment statements is not important , The reverse result is the same .