VHDL implementation of arbitrary size matrix addition operation

This design is VHDL Realize the addition operation of any size matrix
Add two matrices through addition , The results obtained are stored in Buffer in

Use VHDL Language
stay vivado Synthesis and Simulation on

The design code is as follows ：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

– Uncomment the following library declaration if using
– arithmetic functions with Signed or Unsigned values

– Uncomment the following library declaration if instantiating
– any Xilinx leaf cells in this code.
–library UNISIM;
–use UNISIM.VComponents.all;

entity IntMatAddCore is
port(
Reset, Clock, WriteEnable, BufferSel: in std_logic;
WriteAddress: in std_logic_vector (9 downto 0);
WriteData: in std_logic_vector (31 downto 0);-- input two matrix Matrix of any size can be entered
WriteDataB: in std_logic_vector (31 downto 0); – input two matrix Matrix of any size can be entered
ReadAddress: in std_logic_vector (9 downto 0);
ReadEnab