The new version of onespin 360 DV has been released, refreshing the experience of FPGA formal verification function

360 DV Is aimed at FPGA Design solutions for functional verification . It combines full-featured high-performance formal analysis with unique assertion coverage assessment , Eliminate guesswork during quality assertion generation , Effectively improve the productivity of existing design and validation processes . What new experiences will this update bring to the design team ？

One 、DV inspect Function update

● Read write competition check

explain ： As shown in the figure below , The simulation results are not consistent with those of the upper board , This is a synthesis and simulation mismatch problem caused by reading and writing signals in different processes , Now? ,OneSpin New features to check for such problems , Ensure that the simulation results are consistent with the actual situation after synthesis .

● Negative conversion check

explain ： Automatic tagging of unexpected design behavior

● Deadlock / Live lock inspection

explain ： If DUT Into a state that is no longer running （ Auto suspend ）, Then mark... In the inspection results

● newly added Lint Check the item

* Mixed extremum reset

* Mix sync / Asynchronous reset

* blend ( Not ) Block assignment

* Useless state machine position

* An incomprehensible delay

* Repetitive case label

* Multiple drive

* Non constant asynchronous reset value

Two 、 Debug function update

● Modification of the second wave cursor

explain ： It's tedious to calculate the number of events in the waveform interface , And it's easy to make mistakes . Now the second cursor will automatically display the event count of the selected signal , And you can put it in the next / The previous event

● New fault view

explain ： In the course of debugging , Fewer harmful faults , In order to make the fault in the waveform debugging interface , More obvious , It's easier to analyze , The waveform interface will highlight the place where the fault occurs , And provide a simple explanation .

3、 ... and 、 Code language update

● New support for static SystemVerilog class , Using shared functions of classes with static methods / The type is more flexible , Here's the picture , The universal leading zero counter can be used directly

Four 、DV Apps to update

● IEEE-754 2019 Added new Max / Minimum function , and RISC-V The standard forbids IEEE-754 Some of the optional elements in , Now? ,FPU app Of RISC-V Configuration can be seamlessly integrated into RISC-V Of FPU Verification in progress

● Check signal name is supported in register check

explain ： Make sure RTL The signal name matches IP-XACT standard

● Connectivity APPs Custom naming is supported in

● Simplify coverage check reporting

explain ： The coverage state is simplified to D(detected), N(undetected), O(open), To make the result clearer

Original coverage interface

New coverage screen

For more details ：http://www.softtest.cn/