Structure summary of SystemVerilog integrable model

One 、 Structure of integrable model

    If the program is only used for simulation , Then almost all syntax and programming statements can be used . But if the program is used for hardware implementation , Then we must ensure the comprehensibility of the program , That is, the program written can be integrated Into the corresponding circuit structure . It's not comprehensive HDL Statements will be ignored or reported as errors when synthesized with the synthesis tool . As a designer , You should have some understanding of the structure of the integrable model .

    Although different comprehensive tools are right Verilog HDL Support for grammatical structures varies , but Verilog HDL Some typical structures in are clearly supported or unsupported by all integrated tools .

    （1） All integrated tools support the knot structure ：always,assign,begin,end,case,wire,tri,aupply0,supply1,reg,integer,default,for,function,and,nand,or,nor,xor,xnor,buf,not,bufif0,bufif1,notif0,notif1,if,inout,input,instantitation,module,negedge,posedge,operators,output,parameter.

    （2） Structures that are not supported by all integrated tools ：time,defparam,$finish,fork,join,initial,delays,UDP,wait.

    （3） Some tools support structures that some tools do not support ：casex,casez,wand,triand,wor,trior,real,disable,forever,arrays,memories,repeat,task,while.

therefore , To write a comprehensive model , Try to use the structure supported by all comprehensive tools to describe , Only in this way can we ensure the correctness of the design and shorten the design cycle .

Two 、 Principles of establishing a comprehensive model

    Make sure that Verilog HDL The comprehensibility of assignment statements , The following points should be noted during modeling ：

    （1） Do not use initialization statements .

    （2） Do not use descriptions with delays .

    （3） Do not use loop statements with uncertain number of loops , Such as forever、while etc. .

    （4） Do not use user-defined primitives （UDP Components ）.

    （5） Try to design the circuit in synchronous mode .

    （6） Unless it is the design of critical path , Generally, the method of calling gate level components to describe the design is not adopted , It is recommended to use behavior statements to complete the design .

    （7） use always Process blocks describe combinatorial logic , All input signals shall be listed in the sensitive signal list .

    （8） All internal registers should be able to be reset , In the use of FPGA When implementing the design , The global reset terminal of the device shall be used as the overall reset terminal of the system as far as possible .

    （9） Description and modeling of temporal logic , Non blocking assignment should be used whenever possible . Description and modeling of combinatorial logic , You can assign values with blocking , You can also use non blocking assignment . But in the same process block , It is best not to use both blocking and non blocking assignments .

    （10） Not in more than one always Assign a value to the same variable in the process block . However, blocking assignment cannot be used for the same assignment object , Non blocking assignment is also used .

    （11） If you don't want to deduce variables into latches , Then it must be in if Sentence or case The variable is explicitly assigned in all conditional branches of the statement .

    （12） Avoid mixing triggers triggered by rising and falling edges .

    （13） The assignment of the same variable cannot be controlled by multiple clocks , Nor can it be subject to two different clock conditions （ Or different clock edges ） control .

    （14） To avoid the case Statement x Value or z value .

3、 ... and 、 Blocking and non blocking

    It is suggested to use non blocking assignment when modeling temporal logic . Because for blocking assignment , The order of assignment statements has a direct impact on the final comprehensive result , If the designer doesn't pay attention, the comprehensive results will be consistent with the design book The meaning is quite different . If non blocking assignment is used , Then the order of assignment statements can be ignored , Just describe the connection relationship clearly . Such as the following model ：

     always @ （posedge clkA）   //Label  AwA

         … = DataOut;              // read DataOut Value

     always @ （posedge clkA）   //Label  AwB

         DataOut <= …;        // Use non blocking assignment

    If the above model is changed to blocking assignment “DataOut = …”, Simulate these in the written order in the program always sentence , stay clkA At the rising edge ,always sentence AwA Read out DataOut The current value of the , then always sentence AwB Again to DataOut Assign new values to . If you reverse these two always Order of statements （ Or the simulator chooses to reschedule these two always The order in which statements are executed ）, Well, first of all always sentence AwB, This causes the new value to be assigned to DataOut, And then always sentence AwA What you read is the updated DataOut value . This seems to be due to always When all statements can be executed , towards DataOut The assignment of occurs and is completed in zero time . So according to which one to execute first always sentence ,AwA Reads the DataOut Value may be its original value , It may also be its new value .

    Using non blocking assignment can eliminate the dependence of this simulation behavior , At this time , Read DataOut Occurs at the current moment , At the end of the current simulation cycle （ That is, all variable reads have been completed ） The new value Assign to DataOut. In this way, the behavior of the above model is no longer affected always The influence of statement execution order . therefore , In a certain always Statement to assign a value to a variable in this always Read out of statement Variable , Then the assignment statement should be non blocking assignment .