Detailed comparison of Hynix emmc5.0 and 5.1 series

SK hynix e-NAND from NAND flash and MMC The controller consists of .
e-NAND With built-in intelligent controller , Used to manage interface protocols 、 Wear is even 、 Bad block management 、 Garbage collection and ECC.e-NAND Protect data content from sudden power failure of the host .
e-NAND compatible JEDEC The standard eMMC5.1 standard .

One 、 summary
• Bus mode
- Data bus width ：1 position （ Default ）,4 position ,8 position
- Data bus width ：1 position （ Default ）,4 position ,8 position
-MMC Switching clock frequency ：0~200MHz
-MMCI/F Starting frequency ：0~52MHz

• Voltage range
-Vcc(NAND)：2.7V-3.6V
-Vccq（ controller ）：1.7V-1.95V/2.7V~3.3V

• temperature
- Operating temperature （-25℃~+85℃）
- Storage temperature （-40℃~+85℃）

• Other characteristics
-HS400,HS200
-HPI,BKOPS,BKOP Operational control
- pack CMD,CMD line up
- cache , Cache barrier , Cache refresh report
- Partition ,RPMB,RPMB Throughput improvement
- discarded , trim , erase , disinfect
- Write protect , Secure write protection
- lock / Unlock
-PON, sleep / Wake up the
- Reliable write start function , Start partition
-HW/SW Reset
- Field firmware update
- Configurable driver strength
- health （ intelligence ） The report
- Production state awareness
- Safe delete type
- Data strobe board pin , Enhanced data strobe board （ stay eMMC5.1 Bold function is added in ）

Two 、 Power waste
Active power consumption during operation

• Temperature : 25℃
• Average current consumption ：100 ms Above cycle
• Peak current consumption ： The period exceeds 20us
•Vcc：3.3V
•Vccq：1.8V

3、 ... and 、e-NAND new function (eMMC5.0 and eMMC5.1)
1、 eMMC5.0 new function

•HS400 Pattern
e-NAND Support HS400 Signaling , adopt 200MHz Of DDR Clock frequency implementation 400MB/s The speed of the bus .HS400 Patterns only support 8 Bus width of bits and 1.8V Of Vccq. Because the speed is fast , The host may need to have an adjustable sampling point to use reliably DS The pin receives the incoming data ( Read data and CRC Respond to ).e-NAND Support the most 5 Drive strength .

• Field firmware update (FFU)
To download a new firmware ,e-NAND Need to follow JEDEC Standard instruction sequence .SKhynixe-NAND Only manual mode is supported ( I won't support it MODE_OPERATION_CODES). For more details , See the chart and registry below .

• Health （ intelligence ） The report
Use this function to monitor equipment status , Prevent errors and faults . The mainframe can be used EXT_CSD Check the device information as the following registry .

• Production state awareness
This new feature is for eMMC5.0 JEDEC Specification added . To prevent data interruption during equipment welding . For the implementation of this feature ,e-NAND Only manual mode is supported , and PRODUCT_STATE_AWARENESS_TIMEOUT by 0x17（ Maximum ）. For more information , Please refer to the following flowchart and registry .

• Sleep notification
When the host intends to shut down after moving the device to sleep Vcc when , It can use shutdown notification . Some functions have been added to clarify the specification of entering sleep mode when shutdown notification is enabled .

• Safe removal type
This function is used to delete information from physical memory during a purge operation .

2、 eMMC5.1 new function
• Order to line up
e-NAND Manage an internal task queue , The host can queue data transmission tasks to achieve efficient operation .

• Cache barrier
In some cases , The host is not interested in refreshing the data immediately , But it wants to maintain order between different cached data . Flushing can be delayed by the device to some later idle time .
The barrier command avoids long delays by refreshing the command .

• Cache flush report
For devices that refresh cached data in a sequential manner , Cache barrier commands are redundant , And cause unnecessary overhead to the equipment and host .

•BKOP control
This function allows the host to indicate to the device , Hope whether it needs to be written BKOPS_START Field to manually start background operations on a regular basis .

• Secure write protection
Any application running on the host can update the write protection related EXT_CSD Field , Such as USER_WP[171]、BOOT_WP[173], By publishing CMD6、CMD8、CMD28 and CMD29（ Legacy mode ） To issue write protection . However , There are also some weaknesses in the legacy pattern . To prevent unauthorized changes , The host should enter safe write protected mode .

In a safe WP In mode , Only when SECURE_WP_MASK Field is 0x1 when , Can be updated with WP dependent EXT_CSDs(EXT_CSD[171],[173]);

Only RPMB Method update SECURE_WP_MASK Register to provide security ;

Automatic write protection mode is added , The security vulnerability caused by power control security attack is prevented .

•Enhanced strobe
In the enhanced strobe mode data OUT in ,CRC Response and CMD The responses are synchronized with the stroboscopic clock .CMD The time relationship between the response output signal and the stroboscopic clock is the same as that defined by the data output to the stroboscopic clock .
•RPMB Throughput improvement
This feature is proposed for RPMB Write data size , In order to improve the eMMC5.1 Normative RPMB throughput . stay eMMC5.0 Specification ,REL_WR_SEC_C[222] The register should be set to 1( Therefore, the particle size is always 512B).
For reliable writing RPMB Partition , The number of blocks cannot exceed REL_WR_SEC_C x512B The size of . stay eMMC5.1 in , Supported by RPMB The write access sizes are 256B、512B and 8KB.

Four 、e-NAND General parameters
• sequential

• Power supply
stay e-NAND in ,Vcc be used for NAND Core voltage and NAND Interface ;Vccq For controller core and e-NAND Interface voltage , As shown in the figure . The core regulator is optional , Only if the internal core logic voltage is controlled by Vccq Only when adjusting . One Creg The capacitor must be connected to VDDi terminal , To stabilize the regulator output on the system .

e-NAND Support one or more Vcc and Vccq The combination of , As shown in the table 18 Shown .
Available voltage configurations are shown in table 19 Shown .

• Hardware design reference