当前位置:网站首页>Model analysis of establishment time and holding time

Model analysis of establishment time and holding time

2022-07-06 00:23:00 Silly boy: CPU

Build time and hold time model analysis

The starting point is the source trigger D1 Sampling time of , The destination is the destination trigger D2 Sampling time of , It is assumed that the starting point has met the requirements of establishment time and holding time , Now analyze whether the end-point sampling time also meets the requirements .
 Insert picture description here
among

  • Tco: The data is sampled correctly from D End arrival Q The delay of the end , Trigger intrinsic properties , It can't be changed .
  • TDelay:D1 Output to D2 Combinational logic delay and wiring delay at the input .
  • Tsu: Trigger setup time , Inherent properties of triggers , It can't be changed .
  • Th: Hold time of trigger , Inherent properties of triggers , It can't be changed .
  • Tclk: Clock cycle .
  • t1: Assume that the source clock is clka,clka arrive D1 Time delay of .
  • t2:clka arrive D2 Time delay of .

The behavior of triggers : Sampling data when the clock edge arrives D, Deposit the collected data , And output to the Q End , All if no new clock comes along , be Q The output of the terminal is always the last sampled data , Every clock edge , Sample the data once D.

hypothesis clk There is no delay in transmission : Then the rising edge of each clock will arrive at the same time D1 and D2. The beginning of time , The first clock edge D1 Sampling time of , The end of time , The second clock edge D2 Sampling time of . Physical starting point ,D1 The input end of the , Physical end point ,D2 The input end of the .

Set up time to meet ( Focus on data headers ): When the first clock comes , data data From the starting point ① Start transmitting , after Tco arrive ②, after TDelay

原网站

版权声明
本文为[Silly boy: CPU]所创,转载请带上原文链接,感谢
https://yzsam.com/2022/187/202207060015476319.html