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Verilog tutorial (11) initial block in Verilog
2022-07-04 23:59:00 【mb611f1478c9b26】
List of articles
- Preface
- Text
- Grammar format
- initial What is the block used for ?
- initial When the block begins and when it ends ?
- How many... Are allowed in a module initial block ?
Preface
In a simulation, a set of Verilog sentence . These statements are placed in a block . stay Verilog There are two main types of blocks in –initial Block and always block .
Text
Grammar format
initial Block can be understood as an initialization block , stay initial The starting position of the statement in 0 The moment begins to execute , After that, if there is a delay , The next statement is executed after the delay .
The syntax is as follows :
initial
[single statement]
initial begin
[multiple statements]
end
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If initial There are multiple statements in , Then place the begin …end Between .
initial What is the block used for ?
The initial block is not integrable , So it can't be converted into a hardware schematic with digital elements . Therefore, in addition to being used in simulation , It doesn't help much . These blocks are mainly used to initialize variables and design ports with specific values .
Be careful : In chip logic design ,initial Blocks really can only be used for behavioral simulation , But in FPGA In design , Simple use initial The initialization of variables can be integrated .
for example :
reg a, b, c;
initial begin
a = 0;
b = 0;
c = 0;
end
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But we initialize more at the moment of variable definition , This is the recommended usage .
for example :
reg a = 0;
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Or use a reset signal to initialize , But this will increase the burden of generic cabling , You can consciously reduce , Unless you have to .
for example :
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initial When the block begins and when it ends ?
At the beginning of the simulation , In time 0 Unit starts an initial block . Throughout the simulation process , This block of code is executed only once . once initial All statements in the block are executed ,initial The execution of the block ends .
If initial There's just one sentence in the block , So the beginning is the end , The statement is executed to end this initial block , Such as :
The code shown in the figure below has an extra statement , It gives the signal b Assigned some values , But this only happens when the previous statement is executed 10 After units of time . It means a First assigned to a given value , And then in 10 After units of time ,b Assigned to 0.
How many... Are allowed in a module initial block ?
There can be multiple ( Arbitrarily )initial block .
Multiple initial Blocks are executed simultaneously , It's all from the moment 0 Start execution .
The code shown in the figure below has three initial blocks , All the initial blocks start and run in parallel at the same time . However , According to the statement and delay in each initial block , The time required to complete the block may vary .
$finish It's a Verilog System tasks , It tells the emulator to terminate the current simulation .
If the last block has 30 Time unit delay , As shown in the figure below , The simulation will be in 30 Time units end , So it killed all the others that were active at the time initial block .
initial begin
#30 $finish;
end
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Reference material
- WeChat official account : FPGA LAB
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