Understand chisel language thoroughly 03. Write to the developer of Verilog to chisel (you can also see it without Verilog Foundation)

written Verilog turn Chisel The developer of the —— Take combinational logic circuit as an example , contrast Chisel and Verilog Basic syntax （ No, Verilog You can also see the foundation ）

One CPU Or other digital chips , It is essentially a large digital logic circuit , If we design a hardware description language CPU, It is necessary to support the basic components of all digital logic circuits ,Verilog such ,Chisel No exception, of course . In this article, we will Take combinational logic circuit as an example , contrast Chisel and Verilog Basic syntax .

So let's first review the basic units of combinational logic circuits . Combinational logic circuit is a kind of digital logic circuit without state , Its output is only related to input , Basic units except Input signal 、 The output signal outside , Is the Logic gate Formed a gate circuit .

Single bit input / Output and module writing

Input / The output signal is usually binary , One digit input / The output signal can be 0 or 1, Multi bit input / The output signal can be combined into a multi bit binary small signal , According to the specific code / The decoding convention can represent a specific binary number . One bit signal can be called a bit, Multi bit binary signals are called bits.

With single bit Input 、 And the module whose input is directly hardwired to the output is Verilog The expression method in is as follows ：

module module_sample {
    input wire in_sample_bit,	//  One bit wire network data input 
    output wire out_sample_bit	//  One bit wire network data output 
    };
    assign out_sample_bit = in_sample_bit;
endmodule

among ,module and endmodule The part between defines a module ,module_sample For the module name ,input、output Indicates whether the signal is input or output ,wire The signal type is specified , You can omit , because Verilog The default signal in is wire type ,in_sample_bit and out_sample_bit Are all signal names .

And in the Chisel The expression in is slightly different , Let's look at an example ：

import chisel3._

class ModuleSample extends Module {
    
    val io = IO(new Bundle {
    
        val in_sample_bit = Input(Bool())
        val out_sample_bit = Output(Bool())
    })
    io.out_sample_bit := io.in_sample_bit
}

Explain the following ：

1. First we need to import chisel3._ package , bring Scala Support Chisel;
2. Chisel The module implemented in is a class , Inherited from Chisel Built in classes for Module;
3. Chisel The input and output in the module are IO Class , The instantiated variable is a Bundle Example , This Bundle I'll say later , Now it can be simply understood as a structure ;
4. Bundle The instantiated parameters are two signals , Namely Input Classes and Output Class , The instantiated parameters are Bool(), They are Bool Type input / The output signal ;
5. Use input / When outputting a signal , The signals are IO example io Members of , use io.xxxx Method reference of , Use := Operator represents hardwired ;

We can go through getVerilogString Function outputs the Verilog Code , The complete code is as follows ：

import chisel3._

class ModuleSample extends Module {
    
    val io = IO(new Bundle {
    
        val in_sample_bit = Input(Bool())
        val out_sample_bit = Output(Bool())
    })
    io.out_sample_bit := io.in_sample_bit
}

object MyModule extends App {
    
    println(getVerilogString(new ModuleSample()))
}

Output is as follows ：

module ModuleSample(
  input   clock,
  input   reset,
  input   io_in_sample_bit,
  output  io_out_sample_bit
);
  assign io_out_sample_bit = io_in_sample_bit; // @[temp.scala 10:23]
endmodule

You can see , Except for omitted types wire And extra generated but unused clocks 、 Reset signal , Others and Verilog The code is basically the same .

About high resistance state and unstable state （ Skippable ）

What needs to be noted here is ,Verilog There is Four logical states , Respectively 0、1、z and x, Respectively corresponding to low level 、 High level 、 High resistance state 、 The unsteady state , And in the Chisel There are no high resistance states and unstable states .

But this has no effect on us , Because these two logic states are not used in the internal design of most chips , Using this state in the design may bring harm , And only 0、1 The design of simplifies the model , Behavior convenient for analysis and design .

Of course ,Chisel 3.1+ Version of Experimental It also defines Simulation type Analog（ Equivalent to Verilog Medium inout）, Also called black box type （BlackBox Type）, It is used to cover properties such as high resistance state and unstable state . It defines the analog network 、 Three state wire network 、 Two way network and power network （ Yes “ Ground wire ” or “ power cord ” modeling ）. Although it's experimental , But it also means Chisel These features may be better supported in the future , Even if we basically can't use these .

Analog It is a type without direction , So many Analog The type can be through attach Operators connected together . It can also be used. <> Operator join Analog type once , But not many times . such as ：

val a = IO(Analog(1.W))
val b = IO(Analog(1.W))
val c = IO(Analog(1.W))

//  It can be connected like this 
attach(a, b)
attach(a, c)

//  Or even so 
a <> b

//  That's not good , because 'a' Connected many times 
a <> b
a <> c

Multi bit signal

We may be resetting the signal 、 The single bit signal is used in the enable signal , But most of the time, the signal or data we need to process is multi bit . For example, the input signal is two signed integers , The output is the sum of these two integers , Therefore, the hardware design language must support multi bit signals .

Verilog Array is used in to represent multi bit signals , For example, the following modules are implemented 4 Bit unsigned number truncation addition ：

module module_sample {
    input wire [3:0] in_a,	// 4 Signed number of bits in_a
    input wire [3:0] in_b,	// 4 Signed number of bits in_b
    output wire [3:0] out_c	// in_a and in_b And , Overflow truncates the last four digits 
    };
    assign out_c = in_a + in_b;
endmodule

You can see , We use it [3:0] Specifies the width of the signal . If no symbol is specified , be wire The signal of type is unsigned by default , If it's a signed number , You need to use signed keyword . Here is 4 Bit signed number addition ：

module module_sample {
    input wire signed [3:0] in_a,	// 4 Signed number of bits in_a
    input wire signed [3:0] in_b,	// 4 Signed number of bits in_b
    output wire signed [3:0] out_c	// in_a and in_b And , Overflow truncates the last four digits 
    };
    assign out_c = in_a + in_b;
endmodule

and Chisel In, use UInt and SInt Types represent unsigned numbers and signed numbers , Usage and Bool similar , The difference is that you need to specify the signal width . for example ,Chisel in 4 The implementation of the bit signed number addition module is as follows ：

class ModuleSample extends Module {
    
    val io = IO(new Bundle {
    
        val in_a = Input(SInt(4.W))
        val in_b = Input(SInt(4.W))
        val out_c = Output(SInt(4.W))
    })
    io.out_c := io.in_a + io.in_b
}

among ,SInt() Internal 4.W Defines the signal width , The format is Width .W, If not given , It is likely that width reasoning cannot be carried out , The runtime throws Uninferred width for target below. (Did you forget to assign to it?) error . Output Verilog The code is as follows ：

module ModuleSample(
  input        clock,
  input        reset,
  input  [3:0] io_in_a,
  input  [3:0] io_in_b,
  output [3:0] io_out_c
);
  assign io_out_c = $signed(io_in_a) + $signed(io_in_b); // @[temp.scala 11:25]
endmodule

You can see , Although it is not specified whether it is a signed number in the definition of input and output , But in the process of calculation, two 4 Bit inputs are treated as signed operands , So with the front Verilog Defined 4 The bit signed number addition module is also equivalent .

UInt Usage is similar. , I won't go into details here .

Constant

seeing the name of a thing one thinks of its function , A constant is a constant value whose value cannot be changed , Now let's talk about the integer constants in Verilog and Scala Representation in .

Verilog The format of integer in is +/-< A wide >'< Base number >< Numbers >, among +/- Symbol bit , Positive numbers can be omitted ,< A wide > Express Binary system Width , Default 32 position , Then separate with single quotation marks , trailing < Base number > There are four kinds. ：

1. Binary system ：b or B;
2. Decimal system ：d or D Or default ;
3. Hexadecimal ：h or H;
4. octal ：o or O;

for example , The following figures are in Verilog Is equivalent in ：

10
32'd10
32'b1010
32'ha
32'o12

And in the Chisel in , Constants, or literals, are passed through Scala An integer or string is passed to the constructor of the type to get , So Chisel The constants in and Scala Constants in should be distinguished , Examples are as follows ：

//  Unsigned integer 
10.U		//  From decimal Scala Int structure ,10, Binary representation as 4 position 
"ha".U		//  From hexadecimal Scala String construction ,10, Binary representation as 4 position 
"o12".U 	//  From octal Scala String construction ,10, Binary representation as 4 position 
"b1010".U	//  From binary representation Scala character string , still 10, Binary representation as 4 position 

//  Signed integers 
5.S			//  From decimal Scala Int structure , Signed integers 5, Binary representation as 4 position （0101）
-8.S		//  From decimal Scala Int structure , Signed integers -8, Binary representation as 4 position （1111）
5.U			//  From decimal Scala Int structure , Unsigned integer 5, Binary representation as 3 position （101）

//  You can also specify the width of the constant 
8.U(4.W)	// 4 Bit unsigned integer , The value is 8
-152.S(32.W)// 32 Bit signed integer , The value is -152

//  And finally Bool type , That is, single bit constant 
true.B		//  from Scala Boolean type construction , The value is 1, a 
false.B		//  from Scala Boolean type construction , The value is 0, a 

For longer strings , We are Verilog and Chisel Can be separated by underscores in , To increase code readability , however Verilog It is used in numbers ：

32'h_dead_beef	//  stay Verilog At a moderate price 32'hdeadbeef

and Chisel It is used in the string ：

"h_dead_beef".U	//  stay Chisel At a moderate price "hdeadbeef".U

By default ,Chisel The compiler will set the length of each constant to the minimum size that can hold the constant , Include sign bits with sign types , We can also pass .W To specify the , That was demonstrated above .

Let's explain something similar .U and .W This kind of usage （ This paragraph can be skipped until the next section ）：

.W In front is a Scala Integers ,.W Is to convert this integer into a Chisel Objects of width type ;.U In front is a Scala object ,.U That's right Scala Object called UInt Constructor asUInt, such as ：

"ha".asUInt(8.W)     //  Equivalent to "ha".U(8.W)
"o12".asUInt(6.W)    //  Equivalent to "o12".U(6.W) 
"b1010".asUInt(12.W) //  Equivalent to "b1010".U(12.W)

//  Empathy 
5.asSInt(7.W) 		//  Equivalent to 5.S(7.W)
5.asUInt(8.W) 		//  Equivalent to 

We can also use it asUInt This constructor performs cast , But notice Width cannot be specified explicitly ：

val sint = 3.S(4.W)             // 4-bit SInt

val uint = sint.asUInt          //  take SInt Convert to UInt
uint.asSInt                     //  take UInt Convert to SInt

Because there is no width parameter ,Chisel Will expand or truncate as needed , This conversion can also be used in clock types Clock On , But be careful , I won't go into details here .

summary

This article is about Verilog and Chisel Module writing of 、 Basic data types are simply compared with integer constants , Mainly to give you a simple impression .

If you used to write Verilog Of , After reading, I should feel Chisel In fact, it's almost , Including the clock that has not been mentioned yet 、 Register, etc .

Even if you were right before Verilog Do you understand , I should have a preliminary impression here , Even if you simply understand the basic grammar, you can write directly Chisel Module .

The next article begins with , Let's start learning a little bit formally Chisel The grammar and characteristics of , This series must be handled carefully Chisel！