当前位置:网站首页>HDU 5077 NAND (violent tabulation)
HDU 5077 NAND (violent tabulation)
2022-07-06 22:33:00 【Full stack programmer webmaster】
Hello everyone , I meet you again , I'm the king of the whole stack .
The main idea of the topic :Xiaoqiang To write a coding program , Then according to x1,x2,x3 The value of constructs 8 Characters . Now given the requirements generated 8 Characters . ask
say Xiaoqiang At least how many lines of code to write . The code content can only be NAND Operation and return operation , The variables of the operation can be constants .
Their thinking : Enter a total of 256 Medium condition , So violent pruning and beating table , The code for typing tables has been deleted ... So let's think about it . Open one s Array
Said variable , Then two variables at each time for each layer NAND operation .
Roughly three pruning ,dfs When , When variables appear, skip .8 Characters can be calculated directly according to the bit operation of numbers ; The same skip occurs in the previous layer .
#include <cstdio>
#include <cstring>
#include <algorithm>
using namespace std;
const int ans[300] = {1, 5, 6, 3, 6, 3, 7, 4, 7, 8, 4, 5, 4, 5, 4, 1, 6, 3, 7, 4, 7, 4, 9, 7, 8, 8, 7, 5, 7, 5, 7, 4, 7, 8, 4, 5, 8, 8, 7, 5, 8, 9, 5, 6, 8, 8, 5, 5, 4, 5, 4, 1, 7, 5, 7, 4, 8, 8, 5, 5, 5, 7, 6, 4, 7, 8, 8, 8, 4, 5, 7, 5, 8, 9, 8, 8, 5, 6, 5, 5, 4, 5, 7, 5, 4, 1, 7, 4, 8, 8, 5, 7, 5, 5, 6, 4, 8, 9, 8, 8, 8, 8, 5, 7, 11, 9, 8, 9, 8, 9, 8, 8, 5, 6, 5, 5, 5, 5, 6, 4, 8, 9, 8, 8, 8, 8, 8, 7, 8, 9, 9, 9, 9, 9, 10, 9, 5, 7, 6, 6, 6, 6, 7, 6, 9, 9, 10, 9, 10, 9, 10, 10, 7, 6, 7, 7, 7, 7, 9, 7, 5, 7, 6, 6, 7, 6, 7, 7, 5, 6, 2, 3, 6, 6, 4, 3, 6, 6, 7, 6, 7, 7, 9, 7, 6, 6, 4, 3, 7, 7, 7, 6, 5, 7, 7, 6, 6, 6, 7, 7, 5, 6, 6, 6, 2, 3, 4, 3, 6, 6, 7, 7, 7, 6, 9, 7, 6, 6, 7, 7, 4, 3, 7, 6, 5, 6, 6, 6, 6, 6, 7, 7, 8, 9, 5, 6, 5, 6, 2, 5, 2, 3, 4, 3, 4, 3, 7, 6, 5, 6, 2, 5, 2, 5, 4, 1};
int main () {
int cas;
char p[10];
scanf("%d", &cas);
while (cas--) {
scanf("%s", p);
int ret = 0;
for (int i = 0; i < 8; i++)
ret = ret * 2 + p[i] - '0';
printf("%d\n", ans[ret]);
}
return 0;
}Copyright notice : This article is the original article of the blogger . Blog , Do not reprint without permission .
Publisher : Full stack programmer stack length , Reprint please indicate the source :https://javaforall.cn/116988.html Link to the original text :https://javaforall.cn
边栏推荐
- GD32F4XX串口接收中断和闲时中断配置
- OpenCV VideoCapture. Get() parameter details
- Attack and defense world ditf Misc
- 自制J-Flash烧录工具——Qt调用jlinkARM.dll方式
- Installation and use of labelimg
- Memorabilia of domestic database in June 2022 - ink Sky Wheel
- CCNA Cisco network EIGRP protocol
- signed、unsigned关键字
- SQL server generates auto increment sequence number
- 视图(view)
猜你喜欢

机试刷题1

Build op-tee development environment based on qemuv8
![[leetcode] 19. Delete the penultimate node of the linked list](/img/ab/25cb6d6538ad02d78f7d64b2a2df3f.png)
[leetcode] 19. Delete the penultimate node of the linked list

pytorch_YOLOX剪枝【附代码】

RESNET rs: Google takes the lead in tuning RESNET, and its performance comprehensively surpasses efficientnet series | 2021 arXiv

Spatial domain and frequency domain image compression of images

Pit encountered by handwritten ABA

网络基础入门理解

CCNA Cisco network EIGRP protocol

树的先序中序后序遍历
随机推荐
UE4蓝图学习篇(四)--流程控制ForLoop和WhileLoop
Report on technological progress and development prospects of solid oxide fuel cells in China (2022 Edition)
3DMAX assign face map
2022-07-05 stonedb的子查询处理解析耗时分析
Jafka来源分析——Processor
Adavit -- dynamic network with adaptive selection of computing structure
Attack and defense world ditf Misc
go多样化定时任务通用实现与封装
Seata aggregates at, TCC, Saga and XA transaction modes to create a one-stop distributed transaction solution
Lora sync word settings
如何用程序确认当前系统的存储模式?
Hardware development notes (10): basic process of hardware development, making a USB to RS232 module (9): create ch340g/max232 package library sop-16 and associate principle primitive devices
软考高级(信息系统项目管理师)高频考点:项目质量管理
RESNET rs: Google takes the lead in tuning RESNET, and its performance comprehensively surpasses efficientnet series | 2021 arXiv
[Digital IC hand tearing code] Verilog burr free clock switching circuit | topic | principle | design | simulation
Aardio - 利用customPlus库+plus构造一个多按钮组件
Signed and unsigned keywords
重磅新闻 | Softing FG-200获得中国3C防爆认证 为客户现场测试提供安全保障
Netxpert xg2 helps you solve the problem of "Cabling installation and maintenance"
sizeof关键字