USB (XVI) 2022-04-28

The relevant configuration of firmware should be clear before testing , May refer to （ fourteen ）; Check the development environment article to understand Control center and Streamer Use , Use test use Streamer Conduct speed test , Make sure FX3 Running on the 3.0 state , Use Control center Complete the basic reading and writing test . In addition, you should know the board information before testing , Modify the corresponding pin mapping .

1. Reading test

The mechanism of lower machine reading test code is to read it all the time as long as there are a few numbers in the buffer , Until the buffer is read empty . In the read operation, use 16kB By the upper computer （control center） Data distribution , If the data is less than 16kB, Notice when sending , Not for 1024bit Multiple , Otherwise, only when the cumulative data reaches 16kB Can only be collected . At the same time, it has been verified , If the data sent by the upper computer is less than 1024 It can also be done through ILA Collect to . adopt GPIF II Interfaces can be FPGA Read , And it can be captured and verified by logic analyzer . among flag_x_d All signals are sampled . The sampled signal is used in the general formula calculation in the case of local signs . Use vivado burning (.bit) Documents are burned at the same time DEBUG(.ltx) The file will pop up ILA display , The trigger signal can be set to slrd_n Falling edge trigger of , Observe ILA Whether the last data captured is consistent with the data sent by the upper computer , Verify the experimental results . meanwhile Make it clear that a cell of the logic analyzer represents writing or reading a data word .

verilog The code is as follows ：