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(4) UART application design and simulation verification 2 - RX module design (stateless machine)
2022-07-05 23:17:00 【Shaoqing is not in Dali Temple】
Removed state machine RX How to design the module ? First sort out which modules to complete
1) Determine when data is received ? That is to detect start position , By detecting the falling edge, it is determined to start receiving data .—— negedge_detect
2) Determine the time period for receiving single frame data ? Detected from start Bit start , Until the last stop bit is passed . A total of 11 individual bit position , Then again 12 individual bit It can be closed halfway through the bit .——start_recieve_flag
3) Every time bit Count clk, Enter the data receiving area and then start counting , Clear when you leave this area .——baud_cnt
4) Calculation bit Count ,1bit Start bit +8bit Valid data bits +1bit Check bit +2bit Stop bit .—— bit_cnt
5) The data transfer , Data reception of valid data bits ,bit_cnt>=1,bit_cnt<=8——rx_data
6) data verification ,check_mode_bit,^{rx_data,check_mode_bit} == CHECKMODE
//2022.6.30
//edgar.yao
//uart rx blaock
module uart_rx(
input clk,
input rst_n,
input rx,
output[7:0] rx_data,
output rx_data_valid
);
parameter CHECKMODE = 1;
parameter BAUD_NUM = 50_000_000/115200;
//(1)define all
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