当前位置:网站首页>[Tear AHB-APB Bridge by hand]~ Why aren't the lower two bits of the AHB address bus used to represent the address?
[Tear AHB-APB Bridge by hand]~ Why aren't the lower two bits of the AHB address bus used to represent the address?
2022-08-01 07:28:00 【IC my uncle】
本章目录:
0. 前言
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接下来回到正题===>
Update this blog because I encountered a problem in the process of doing the project,The following is a brief description:
constraint haddr_constr{
(hsize == HWORD) -> (haddr[0] == 1'b0);
(hsize == WORD) -> (haddr[1:0] == 2'b0);
solve hsize before haddr;
}
At first it wasn't very clear why the restriction was in place,I understand after studying,以下是我的个人理解,希望大家批评指正!!!
1. The role of the lower two digits
AHBThe signal conveyed by the lower two bits of the bus is not used to represent the address of the data,The data address is represented by the remainder after removing the lower two bits30位.如下图所示,HSIZEDetermines the type of transfer,是WORD、BYTE还是HALFWORD;在地址阶段,HADDRand the lower two digits of HSIZEThe signals together determine the transmission,Where are they stored on the data bus.
You can observe the picture to find out,HSIZE=00时,means that the transmission isBYTE,8位的,那么,HADDRIt's up to you to decide which octet you are storing;同理,HIZE=01,那你HADDRThe lower bit will not work,就是0;同理,HSIZE=10时,传输一个WORD,32位,那你的HADDRBoth are0,That's whyADDRThe lower two bits are restricted.
2. 为什么ADDRThe lower two bits are used to store other information,rather than address information?
The main reason is that the data bus is 32bit,The process of data interaction is based on32bit(4个字节)来进行的,If you only need to read and write one or half a word,can be obtained by the above method.
因此,CORTEX-M核中,The offset of the address always starts with “4”Offset in units,Therefore, the lower two bits have not been used,So it is used to store other information.如下图所示,地址每次偏移4字节,The lower two digits are useless.
不论怎么样,The lower two bits are never used to update the address,Because every time4为单位递增,That is, it starts to increase from the third digit.
2. 关于solve…before…的说明
之前在学习SV的时候,Never seen such a constraint,今天学习一下
(The previous constraints can refer to another blog:传送门)
SystemVerilog中随机变量在常见的约束(符号约束、inside约束、条件约束、内嵌约束)条件下,其随机值出现的概率是均等的.但是 使用solve…before约束后,将会改变随机数值的出现几率,使得某些特定的取值情况更易出现.
2.1 没有solve…before…
class transaction;
rand bit a;
rand bit[1:0] data;
constraint c1{
a -> data==3'h3;} //条件约束
endclass
module gen_data;
initial begin
transaction tr=new() ;
for(int i=0; i<10; i++ ) begin
tr.randomize() ;
$display("a= %0d, data= %0d",tr.a, tr.data) ;
end
end
endmodule
The above one just adds a conditional constraint,结果如下:
打印结果如下:
a= 0, data= 2;
a= 0, data= 2;
a= 0, data= 3;
a= 0, data= 1;
a= 0, data= 0;
a= 0, data= 2;
a= 1, data= 3;
a= 0, data= 3;
a= 0, data= 1;
a= 0, data= 1;
due to the existence of conditional constraints,当a=1,data只能为3;而a=0,data可取0,1,2,3四种组合,所以共有5种组合,Each combination has the same probability of occurrence,即1/5,如下表:
2.2 加上solve…before…
class transaction;
rand bit a;
rand bit[1:0] data;
constraint c1{
a -> data==3'h3; //条件约束
solve a before data;} //在给出dataRandom values are given firsta的随机值
endclass
module gen_data;
initial begin
transaction tr=new() ;
for(int i=0; i<10; i++ ) begin
tr.randomize() ;
$display("a= %0d, data= %0d",tr.a, tr.data) ;
end
end
endmodule
Except for one conditional constraint,还增加了solve…before…,The probability of a random outcome will change.
打印结果如下:
a= 1, data= 3;
a= 0, data= 2;
a= 0, data= 3;
a= 0, data= 1;
a= 1, data= 3;
a= 0, data= 2;
a= 1, data= 3;
a= 0, data= 3;
a= 0, data= 1;
a= 0, data= 1;
由于 solve a before datathe existence of constraints,随机变量awill be assigned a random value first,a为1或0的概率为1/2,接下来再为dataRandom variables are assigned random values,Its probability depends on a的值,如下表:
注意:randcType variables are not allowedsolve…before约束;
参考文献
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