[Digital IC manual tearing code] Verilog asynchronous reset synchronous release | topic | principle | design | simulation

Preface

This series aims to provide 100% Accurate numbers IC Design / Verify the title of the hand tearing code link , principle ,RTL Design ,Testbench And reference simulation waveform , The content of each article is checked by simulation . The quick navigation links are as follows ：

Odd frequency division
Even frequency division
Semi integer batch
decimal / Fractional frequency division
Sequence detector
Mode three detector
Beverage machine
Asynchronous reset , Simultaneous release
Edge detection （ Rising edge , Falling edge , On both sides ）
Full adder , Half adder
Gray code to binary
single bit Cross clock domain （ Two beats , Edge synchronization , Pulse synchronization ）
Sync FIFO

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Asynchronous reset synchronous release problem

Use Verilog Code , Complete the design of asynchronous reset and synchronous release circuit

The principle of asynchronous reset and synchronous release

One with asynchronous reset end DFF workflow

If one DFF The reset value of is 0, that rst_n=0 When the signal comes , The DFF Reset , When rst_n=1 When the signal comes , The DFF Normal work .

Possible problems

When rst_n The signal returns 1 Time and clk When the signal coming from the rising edge is very close ,DFF Metastable state may be output , The reason why the signal cannot be recognized is 1 still 0

terms of settlement

Asynchronous reset : Yes 0 The reset signal of is not processed , Let it reset normally asynchronously
Simultaneous release : Yes 1 Make two beats of the reset signal , Align the edge of the clock when it is pulled up , In order to avoid metastable state

Sequence diagram of asynchronous reset and synchronous release

RTL Design

module rst_asy(clk,rst_n,rst_out);

input clk;
input rst_n;
output reg rst_out;

reg rst_r1;

[email protected](posedge clk or negedge rst_n)
if(!rst_n)
begin
rst_out<= 1'b0;
rst_r1 <= 1'b0;
end
else
begin
rst_r1 <= rst_n;
rst_out <= rst_r1;
end

endmodule

Testbench Code

`timescale 1ns /1ps
module rst_asy_tb();
reg clk ;
reg rst_n;
wire rst_out;

rst_asy u1(.clk(clk),.rst_n(rst_n),.rst_out(rst_out));

always #5 clk = !clk;

initial
begin
clk = 0;
rst_n = 1;
#7
rst_n = 0;
#5
rst_n = 1;
#30
$stop;
end

endmodule

Simulation analysis

rst_n After re raising ,rst_out Wait for the register to save twice before output , Metastable state is avoided , Design establishment