How to become a senior digital IC Design Engineer (1-6) Verilog coding Grammar: Classic Digital IC Design

-- adder (Adder)： Consider carry overflow
assign o_sum[DATA_WIDTH:0] = i_parta[DATA_WIDTH-1:0] + i_partb[DATA_WIDTH-1:0];
-- Half adder (Half-Adder)(DATA_WIDTH == 1)： No carry input (DATA_WIDTH == 1)
assign {o_carry, o_sum[DATA_WIDTH-1:0]} = i_parta[DATA_WIDTH-1:0] + i_partb[DATA_WIDTH-1:0];
-- Full adder (Full-Adder)(DATA_WIDTH == 1)： There is a carry input (DATA_WIDTH == 1)
assign {o_carry, o_sum[DATA_WIDTH-1:0]} = i_parta[DATA_WIDTH-1:0] + i_partb[DATA_WIDTH-1:0] + i_carry;

The comparator (Comparator)
assign equal   = (compa == compb) ? 1'b1 : 1'b0;
assign bigger  = (compa >= compb) ? 1'b1 : 1'b0;
assign smaller = (compa <= compb) ? 1'b1 : 1'b0;

Selectors (Selector)(Arbiter)(Multiplexor)(MUX)
// Three implementation methods are simply given ：
// The way 1：
assign result = sel ? dina : dinb;
// The way 2：
assign result = ({(DATA_WIDTH){sel}} & dina[D