[FPGA tutorial case 9] design and implementation of clock manager based on vivado core

FPGA Tutorial directory

MATLAB Tutorial directory

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1. Software version

vivado2019.2

2. Theoretical knowledge of this algorithm

        In the last course , We learned the clock divider based on counter , But the number of frequency division is limited by , And in the FPGA During the design process , Often need some special frequency clock . Using a frequency divider based on a counter cannot achieve , You need to pass vivado The clock provided IP Nuclear to achieve . stay vivado The clock of IP Nuclear configuration ,IP The nuclear name is Clocking Wizard, Directly in IP Catalog Search in .

        below , We go through Clocking Wizard Realize the output of several different frequencies .

3. System design and implementation

stay vivado in , New as follows IP nucleus