Abnormal mode of ARM processor

1、ARM The processor has various exception modes , For response ARM Different states appear . When something unusual happens , Will then enter the relevant exception vector , meanwhile CPSR The register of will also be set to the specific mode .

example ： When there is an interruption , No matter what kind of interruption , Will jump to 0x18 This main entrance address （ It could be 0xFFFFFF18, Look at the virtual address of the system initialization , It doesn't matter ）, Then execute the specific interrupt registration function through the interrupt number .

At the same time, I will put CPSR The register is set to the corresponding mode .

When switching from one mode to another , You need to put the previous mode HW context Save up , For example, from user mode to kernel mode , Because in the new mode , Memory area division is different . Here's the picture , The general register in each mode is the same , In two modes , It can be used to transmit information , But like sp,lr Space related registers will be independent .

2、 When something unusual happens , How to enter exception mode

2.1、 In the kernel boot phase , Initialize the exception vector table .

start_kernel
    setup_arch
        early_trap_init

void __init early_trap_init(void *vectors_base)
{
	unsigned long vectors = (unsigned long)vectors_base;
	extern char __stubs_start[], __stubs_end[];
	extern char __vectors_start[], __vectors_end[];
	unsigned i;

	vectors_page = vectors_base;

    ......

	/*
	 * Copy the vectors, stubs and kuser helpers (in entry-armv.S)
	 * into the vector page, mapped at 0xffff0000, and ensure these
	 * are visible to the instruction stream.
	 */
	memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start);
	memcpy((void *)vectors + 0x1000, __stubs_start, __stubs_end - __stubs_start);

    ......
}

The exception vector address is saved in vectors_base Variable (CONFIG_VECTORS_BASE=0xffff0000) in .

Exception vector address __vectors_start stay entry-armv.S - arch/arm/kernel/entry-armv.S - Linux source code (v5.16.9) - Bootlin Implement initialization .

At compile time , The address has been determined

grep "__vectors" System.map -nR

 

When it starts , You can see the address distribution of the exception vector .

2.2、 When something unusual happens , Jump to the exception vector entry __vectors_start, Different exceptions correspond to different offsets , From the picture 1 It can be seen that software interrrupt Corresponding to the third term of the anomaly vector , namely W(ldr)    pc, .L__vectors_start + 0x1000 Corresponding software interrupt Entrance .

.L__vectors_start:
	W(b)	vector_rst
	W(b)	vector_und
	W(ldr)	pc, .L__vectors_start + 0x1000
	W(b)	vector_pabt
	W(b)	vector_dabt
	W(b)	vector_addrexcptn
	W(b)	vector_irq
	W(b)	vector_fiq

	.data
	.align	2

	.globl	cr_alignment

  Subsequently, it will jump to the specific exception vector processing process according to the macro definition .

	.macro	vector_stub, name, mode, correction=0
	.align	5

vector_\name:
	.if \correction
	sub	lr, lr, #\correction
	.endif

	@
	@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
	@ (parent CPSR)
	@
	stmia	sp, {r0, lr}		@ save r0, lr
	mrs	lr, spsr
	str	lr, [sp, #8]		@ save spsr

	@
	@ Prepare for SVC32 mode.  IRQs remain disabled.
	@
	mrs	r0, cpsr
	eor	r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
	msr	spsr_cxsf, r0

	@
	@ the branch table must immediately follow this code
	@
	and	lr, lr, #0x0f
 THUMB(	adr	r0, 1f			)
 THUMB(	ldr	lr, [r0, lr, lsl #2]	)
	mov	r0, sp
 ARM(	ldr	lr, [pc, lr, lsl #2]	)
	movs	pc, lr			@ branch to handler in SVC mode
ENDPROC(vector_\name)