Chapter 6 data flow modeling - after class exercises

After-school exercises

• Verilog describe

  //  Subtracter module 
  module sub(
  	output D,
  	output B,
  	
  	input x,y,z
  );
  
  // Output D Logical expression 
  assign D = (~x && ~y && ~z) || (~x && y && ~z) || (x && ~y && ~z) || (x && y && z);
  
  
  // Output B Logical expression 
  assign B = (~x && y) || (~x && z) || (y && z);
  
  endmodule
  

• Simulation
  

• The simulation result is much worse than the actual , Some netizens can help to see what's wrong with the code , I haven't found it for a day .