[quick start of Digital IC Verification] 22. Ahb-sramc of SystemVerilog project practice (2) (Introduction to AMBA bus)

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One 、 Description of content

• AMBA Bus Overview
• AHB（ A top priority ）
• APB
• Different IP The interconnection between

notes ：AMBA Bus except APB and AHB outside , also ASB, But it's used less , So this is no longer the focus ！ in addition , We AHB-SRAMC The project only uses AHB Slave On the side , So it's not necessarily that AHB Only when you are proficient can you do this project . As a matter of fact slave Speaking of , Only AHB A simplified version of the protocol ：AHB-Lite.

Two 、AMBA Bus Overview

2.1、 Introduction to system bus

• Each module in the system chip （IP） There needs to be an interface between
• Bus as a subsystem between share The communication link of
  • Share the words , Every slave Will divide the address space
  • In case of direct connection （ Point to point communication ）, There is no need to divide the address space , But the cost is high and it is not easy to expand
• advantage
  • Low cost
  • Convenient and easy to use （ Expandable ）
• shortcoming
  • Can cause Performance bottleneck （ Involving command allocation 、 Queuing and conflict problems ）

2.2、AMBA 2.0

• Advanced Microcontroller Bus Architecture

  • On chip bus standard

• Three kinds of buses are defined

  • AHB（Advanced High-performance Bus）
    • In practice, more variants are used ：AHB-Lite
  • ASB（Advanced System Bus）【 Understanding can 】
  • APB（Advanced Peripheral Bus）
    • Use in Slave in

• AMBA2.0 Upgrade to AMBA3.0 Added AXI agreement , The main application scenario is complex high-speed system .

2.3、AMBA The development history

• AMBA 1.0
  • ASB and APB
• AMBA 2.0
  • AHB,ASB and APB
• AMBA 3.0
  • AMBA Advanced eXtensible Interface（AXI）
• AMBA 4.0
  • AXI Coherency Extensions（ACE）【 Multi core consistency 】

2.4、 A typical AMBA 2.0 System

notes ： What we want to verify is AHB-SRAMC modular , That is to say AHB The data of the interface is converted to SRAMC And then write it in , So study AHB Is a must ！

• Processors and other main devices / Slave devices can be replaced

2.5、AMBA2.0 AHB

• High speed bus （ in the light of APB）、 High performance
• 2 Stage pipeline operation
• It can support multiple bus masters （ There is no limit to the quantity ）
• Support burst transmission （ real Burst Transmission is carried forward in AMBA3.0 Of AXI）
  • AMBA 13’00
• Bus bandwidth ：8/16/32/64/128 bits（32 bits Most used ）
• The rising edge triggers the operation

notes ：AHB be relative to APB Promotion , It mainly lies in two-stage flow ！

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• Q： What is? Burst transmission ？

A： The command of the bus is nothing more than address （ADDR） And data （DATA）. During bus transmission ,single The timing regulation is relatively dead , It takes two beats to complete the address and timing transmission , As shown in the figure below .

Generally, the bus bandwidth is 32bits, That is, you can read 4 Data of addresses . For tradition single transmission , It needs to be sent in the first address cycle ADDR = 0x50, You can read the address in the second data cycle 0x50/0x51/0x52/0x53 Composed of 32 Bit data . I want to read the next 4 Address data , It needs to be sent in the first address cycle ADDR = 0x54, You can read the address in the second data cycle 0x54/0x55/0x56/0x57 Composed of 32 Bit data . Read it like this , Total cost 4 pat .

and Burst The transmission wants to read the above 2 individual 32 Bit data , It needs to be sent in the first address cycle ADDR = 0x50 and INC2（ Indicates that you need to start from 0x50 Read this address consecutively 2 individual 32 Bit data ）, Then you can read one in the second data cycle 32 Bit data , Read another one in the third data cycle 32 For data , Total cost 3 pat .

Empathy , Read more N Data , Then send it in addition to the sending address INCN that will do , Total needs N+1 pat .

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• Q：2 What does stage pipeline operation mean ？

A： Pipeline operation is directly reflected in the address 1 At the time of sending , You can read the address 0 Corresponding data , As shown in the figure below .

2.6、AMBA2.0 APB

• Low speed bus 、 low power consumption
• The interface is simple
• stay Bridge Latch address signal and control signal in
• Applicable to a variety of peripherals （ Because peripherals are interfaces made according to other people's specifications , It must be able to hang up ）
• Rising edge trigger

2.7、AHB Part of the

notes ： The following components are not all SoC Need to be .

• AHB Main equipment （master）
  • launch Once read / Write operations
  • Only one master device is allowed to use the bus at one time
  • CPU、DMA、DSP…
• AHB Slave device （slave）
  • Respond to Once read / Write operations
  • adopt Address mapping To choose which slave device to use
  • External memory controller EMI、APB bridge
• AHB Arbiter （arbiter）
  • Allow a master to control the bus
  • stay AMBA The arbitration algorithm is not defined in the protocol
    • master Is based on fair polling RR Dispatching principle , Or according to the absolute priority SP Dispatching principle ？
    • In actual development , We use RR More
• AHB Decoder （decoder）
  • Determine which slave device to choose through address decoding

2.8、APB Part of the

• AHB2APB Bridge

  • All addresses can be locked 、 Data and control （ Read write control ） The signal
  • Perform secondary decoding to generate APB Select the signal from the device

• APB All other modules on the bus are APB Slave device （ There is no master device ）

2.9、AMBA Other relevant issues of the agreement

• Process independent （ What the protocol realizes is logic , namely RTL Code ）
• Electrical characteristics are not defined （ What is defined is only the logical temporal relationship , And the chip is used internally , Voltage independent ）
• Define timing only at the clock cycle level
  • Provide timing （ Here refers to the physical implementation timing , Don't pay too much attention ） The parameters depend on the adopted process and working frequency
  • give an example ： Not to say that APB Can only run 100M, And the agreement does not stipulate APB It has to be for 100M, You need to determine the frequency of operation according to the selected process and the performance requirements you want to achieve . If you choose 16nm You can run to 300M, choose 65nm You can run to 100M！【 summary ： It is related to practical application , It has nothing to do with the provisions of the agreement .】

2.10、 example ：DMA

notes ： The following example code is pseudocode .