FPGA learning notes: vivado 2019.1 add IP MicroBlaze

Preface

• At present FPGA omnipotent , Can add MCU The core of , That is, it can be embedded in the core of a single chip microcomputer , When a single-chip computer is used , Add here MicroBlaze, This is RISC The core of , Not familiar yet , Estimate and ARM perhaps RISC-V This level of kernel architecture is similar

• Development board ：【 The punctual atoms 】 Vinci Pro FPGA Development board ,FPGA The model of the chip is ：Xilinx Of xc7a35tfgg484-2

• IDE : Xilinx Of Vivado 2019.1

add to 【MicroBlaze】

• MicroBlaze IP The addition of , I follow Xilinx Official video operation , Take a study note here , Just want to know about this embedded in FPGA Medium MCU kernel , How to develop and use

• establish Vivado After empty project , Click on 【IP INTEGRATOR】 Under the 【Create Block Design】, in other words , MicroBlaze As a IP Nuclear way to join the project

• stay 【Diagram】 window , Click on the right 【Add IP…】, Or click on the window toolbar 【+】, add to IP nucleus

• Xilinx Of IP Many nuclei , You can enter MicroBlaze , select 【MicroBlaze】, Double click the mouse after selecting

• add to MicroBlaze IP The interface behind the core , You need to add others 【 peripherals 】, Such as reset Pin Serial port and so on

• Click on above 【Run Block Automation】

• here You can simply modify the configuration of the kernel , Such as RAM size , And so on

• 【Run Block Automation】 after , I found that something was added

add to GPIO peripherals

• The single chip microcomputer must have a pin control ,gpio It's also a IP nucleus , Add method and add to 【MicroBlaze】 The method is the same , choice 【AXI GPIO】

• add to 【AXI GPIO】 After the effect of , By default, there is no connection with 【MicroBlaze】 Connect

add to UART A serial port IP Core is used for serial port printout

• Add method and add GPIO equally , Add here 【AXI Uartlite】

• add to 【AXI Uartlite】 IP After the core , Still independent , With no 【MicroBlaze】 Connect
  

• Double click on the added 【AXI Uartlite】 example , You can see uart Default properties of serial port
  

Summary

• This paper studies how to add 【MicroBlaze】、【AXI GPIO】、【AXI Uartlite】FPGA IP Nuclear Methods

• Later, we will continue to study how to integrate the above IP nucleus , Connect , Form a Embedded MCU

• Keep learning 【MicroBlaze】 Development and use methods of