SPI master RX time out interrupt

background ： test spi Of time out interrupt , The board A master rx, The board B slave tx.master Set to timeout interrupt TIME OUT.

slave Send data ,master Timeout interrupt is not triggered . The image is very accurate , I began to worry that there was a problem with the function of the board , But the simulation is ok . It should be a setup problem .
The simulation told me , eliminate fifo Will clear time out register . So I cleared it once during initialization , It will not be cleared later flfo. But in fact, such waveforms are not correct , Is it slave How to send data to master. And still can't trigger interrupt , If I set it to done Interrupt can trigger . But it's not what we want time out It's broken . The simulation told me again rx trigger level It's empty , Setting data will trigger , It is also invalid after setting , Later, it was found that this bit has a numerical limit , Not too big , Turn into 0. Setting to the correct number will not trigger the interrupt . The simulation tells me again , When transmitting data, there is a lot of data to receive ,cs Keep pulling down , It will cause the board to think that it is still receiving data , Will trigger rxready interrupt , instead of time out interrupt . The reason why we need to receive a lot of data , It's because of my master Set up SPI_DataLen by 512(bits) 了 . Explain in the document ：
Tx/Rx length
Spi During transmission , Effective SCK Count
It also indirectly reflects the length of data sent or received .
So when I set up datalen by 8 in the future , Can trigger normal TIME OUT It's broken .

Later on time out Interrupted document , I found that I didn't read the document in detail . In fact, the author writes very clearly .
When a transmission ends ,rx fifo There's data in , But the amount of data is not enough to trigger rx trigger level when , Over a certain period of time , It will trigger time out register . If it's cleared fifo It will definitely clear the tone time out Counter .

So to test time out, need
1、 The interval between sending data is long , Long enough to trigger after receiving data TIME OUT Then clear away fifo.
2、 The amount of data is less than rx trigger level, And will not trigger too much rx ready interrupt .

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