SPI and IIC communication protocol

One 、IIC

1.I2C Introduction to bus

        I2C（Inter-Integrated Circuit , Internal integrated circuits ) Bus is a kind of bus developed by Philips Philip The serial bus developed by the company . It's two serial buses , It consists of a data line （SDA） And one   Clock line （SDL） form .I2C Multiple can be connected to the bus I2C equipment , Each device has a unique address identification . There can only be one master at a time , Others are slave devices . Usually MCU Control as a main device , Peripherals act as slave devices .

2.I2C Hardware circuit

3.I2C agreement

 I2C There are three status signals : Start signal 、 End signal and answer signal

Start signal ：SCL For high voltage ,SDA Jump from high level to low level , Indicates the start of communication .

End signal ：SCL For high voltage ,SDA Jump from low level to high level , End communication .

Answer signal ： Receiving data IC After receiving a byte of data , Send data to IC To emit a specific low-level pulse , Indicates that data has been received .

        In the process of data transmission ,SCL The clock is controlled by the main device ,SCL Read data when it is high SDA The data of ,SCL When it's low , Main equipment changes SDA The data of is ready to be transmitted to the next bit . Data is transmitted from high order , When transmitting 8 Behind you , The master device will release SDA Bus . If the data is received correctly from the device , Then the slave device will be pulled down SDA Bus , Then a reply signal is generated . If the slave device makes an error , Do not lower SDA Bus , Because of the pull-up resistance ,SDA The level of will become high , It is a non reply signal . Data transmission always starts with a start signal , Terminate the transmission with an end signal , Multiple bytes of data can be transmitted in the middle .

Two 、SPI

1.SPI brief introduction

SPI（Serial Peripheral Interface）, Serial peripheral interface , A high-speed , full duplex , Synchronous communication bus . There are only four wires on the pins of the chip .

MISO：  Main device data input , From the device data output .
MOSI： Main device data output , Input data from the device .
SCK：  Clock signal , It is controlled by the master .
NSS（CS）：  Select the signal from the device , Controlled by the main equipment . When NSS For low level, select slave device .

        As follows, the master device communicates with multiple slave devices , among SCK,MOSI,MISO It's connected ,NSS Receive different IO Pin control . If the master device wants to communicate with the slave device, first pull down the corresponding slave device NSS Pin enable . Default state IO1,IO2,IO3 All high level , When master and slave devices 1 When communication , Pull it down IO1 Pin enable slave device 1. And slave devices 2,3 Do not enable , No response .

2.SPI Sequence diagram

        Every time the transmission starts , The master device first pulls down the chip selection signal line of the slave device NSS, Select the slave device to be transmitted .SCK The clock line transmits one bit of data after sending a clock cycle .MOSI Main out from in , The data is controlled and sent by the main device , Receive from the device .MISO The data of is sent by the slave device , The main device receives . therefore SPI Transmitting a byte is equivalent to exchanging a byte between the master device and the slave device .

SPI There are only master mode and slave mode , There is no saying about reading and writing , Because essentially every time SPI It's the master-slave device exchanging data . in other words , If you send a data, you will receive a data ; If you want to receive a data, you must also send a data first .

According to the clock polarity （CPOL） And phase （CPHA） Different ,SPI There are four working modes .

Clock polarity (CPOL) Defines the clock idle state level ：

    CPOL=0 Low level when the clock is idle

    CPOL=1 High level when the clock is idle

Clock phase (CPHA) Define the data collection time .

    CPHA=0: At the first jump edge of the clock （ A rising or falling edge ） Data sampling .

    CPHA=1: At the second jump edge of the clock （ A rising or falling edge ） Data sampling .