[esp32 learning-2] esp32 address mapping

1. This article begins with esp32 Technical reference manual A description in

   

   1.3.2.4 Internal SRAM 1
   Internal SRAM 1 The capacity of is 128 KB, It can be divided into two CPU Via data bus 0x3FFE_0000 ~ 0x3FFF_FFFF Reading and writing ,
   Can also be two CPU Via instruction bus 0x400A_0000 ~ 0x400B_FFFF Reading and writing .
   Instruction bus address and data bus address access word It's in reverse order . The address ：
   0x3FFE_0000 And 0x400B_FFFC Access the same word
   0x3FFE_0004 And 0x400B_FFF8 Access the same word
   0x3FFE_0008 And 0x400B_FFF4 Access the same word

   The puzzle is why inter SRAM 1 Access different addresses through the data and instruction bus , Get the same content ？ Why is this design ？ What are the benefits ？
   Search for information , Finally found Accurate answer ： It can be customized IRAM and DRAM Size .（ At the same time, it also solves ,esp32 Inside ram How to divide and use ）

2. ROM0 Why do I need Remap：

   1.3.2.1 Internal ROM 0
   Internal ROM 0 The capacity of is 384 KB, Can be two CPU Via instruction bus 0x4000_0000 ~ 0x4005_FFFF Read .
   visit ROM 0 The head of the 32 KB The address of （0x4000_0000 ~ 0x4000_7FFF） Can be Remap To Internal SRAM 1 One of them
   branch , This part was originally addressed 0x400B_0000 ~ 0x400B_7FFF visit . When remapping , this 32 KB SRAM Can no longer be addressed
   0x400B_0000 ~ 0x400B_7FFF visit , however It can be used by data bus (0x3FFE_8000 ~ 0x3FFE_FFFF） visit . The way to do it is
   There are two CPU Configure a register , That is to say PRO_CPU Set up DPORT_PRO_BOOT_REMAP_CTRL_REG The register of
   bit 0 Or for APP_CPU Set up DPORT_APP_BOOT_REMAP_CTRL_REG The register of bit 0.

   There is no explanation on the Internet , I understand it ：
   rom0 As an instruction space, there are 384KB（ It's already very big ）, The allocated address space will not be fully used , Can pass remap The way , take rom The address of is mapped to ram The address of . This will speed up First level bootstrap Operation of .

Strongly recommended relevant information ：
1 Memory address mapping
2 Flash state