The most complete is an I2C summary

Bloggers will I2C spec The article is summarized into one article , Directory as follows

I2C Introduction
I2C Architecture
I2C Transfer
I2C Synchronization And Arbitration
I2C Hs-mode

1、I2C Introduction

1、I2C history

1. I2C：Inter-Integrated Circuit, Integrated circuit bus .

2. I2C yes Philips The company in 1982 The year is the mainboard 、 Embedded system （ Short distance ） A simple design 、 Two way two wire synchronous serial bus .

3. Philips The semiconductor division is now NXP.

4. I2C Where is your patent 2006 year 11 month 1 The date has expired , You can use it for free .

5. Intel 1995 , launched in I2C Compatible bus （System Managerment Bus）, namely SMBus or SMB

6. The latest version I2C spec v.6 On 2014.04.04 Introduction .

2、I2C The future of

1. MIPI The association is in 2014 It was finalized around I3C (improved Inter Integrated Circuit) standard ,I3C stay I2C A superset of functions is established on the specification of , Support high transmission rate mode .

2. At present, whether it is Soc manufacturer , still device manufacturer , Have started or are moving towards I3C excessive .

3. I3C spec Yes 2016 edition 、2018 edition , The latest is 2021 edition (446 page ).

3、I2C The speed of

1. I2C How to read ：“I Fang C”、“I-squared-C”、"I two C"

2. I2C It's a low speed 、 Serial bus , Yes SDA( Serial data line ) and SCL( Serial clock line ) Two signal lines , Half duplex communication .

The communication speed is as follows ：

• Bidirectional bus:

1. Standard-mode (Sm), 100 kbit/s

2. Fast-mode (Fm), 400 kbit/s, Use in sensor、carema、touch etc. .

3. Fast-mode Plus (Fm+),1 Mbit/s

4. High-speed mode (Hs-mode),3.4 Mbit/s, Use in NFC、buck&boost etc.

• Unidirectional bus:

1. Ultra Fast-mode (UFm),5 Mbit/s

Speed by SCL decision , Different modes have different requirements for rising edge , The slope of the rising edge is affected by the pull-up resistance and the equivalent capacitance .

4、I2C It is a multi master-slave architecture bus

1. I2C Both reading and writing are done by master Start from the end .

2. I2C Every communication byte（8bits） Need to be slaver End response ACK/NACK As a response to .

3. many master The arbitration mechanism needs to be introduced at the end .

4. slaver The terminal is distinguished by the device address , Yes 7bits and 10 bits Equal address , There is another kind. 8bits Address , It's actually 7bits + Read write bit .【 among 7 Bit address = Type and model （4bit）+ Address code （3bit）】

5、I2C How many devices can be attached to the bus ？

7-bit address ：2 Of 7 Power , Can hang 128 Devices .

10-bit address ：2 Of 10 Power , Can hang 1024 Devices .

however I2C Provisions of the agreement , The capacitance on the bus cannot exceed 400pF. All pins have input capacitance ,PCB There will also be parasitic capacitance on the , So there will be a limit . The empirical value in the actual design is probably no more than 8 Devices .

The reason why the bus specifies the capacitance , Because I2C The use of GPIO Generally, it is an open drain structure , External resistance pull-up is required , The resistance and bus capacitance create a RC time-delay effect , The larger the capacitance, the slower the edge of the signal , It may bring signal quality risk （ Square wave becomes triangular wave ）. The faster the transmission speed , The smaller the signal window , The rising edge and falling edge require shorter and steeper time , therefore RC The product must be smaller .（ It can be understood that the output high level is to charge the capacitor , The greater the capacitance , The slower the charge ）

Be careful , To put spec The specified reserved equipment address is removed , The following address is reserved ：

note： Is written two groups, Not just eight ,0000 XXX and 1111 XXX Series addresses are reserved .

note： Be careful 1111 1XXX yes Hs-mode master code,1111 0XXX yes 10-bit slave addressing, Bloggers will talk later .

6、 Define terms

2、I2C Architecture

I2C Adopted GPIO Generally, it is in open drain mode , Support lines and functions , But the open drain mode cannot output high level , So it needs to be pulled up externally .Vdd May adopt 5V、3.3V、1.8V etc. , The power supply voltage is different , The pull-up resistance is also different .

It is generally believed I2C On the bus , lower than 0.3Vdd Low level , higher than 0.7Vdd High level .

I2C Each device attached to the bus in the protocol has a unique static device address .

Idle ,I2C Both wires on the bus are high level , Because there is a pull-up resistor .

1、 Push pull structure and open drain structure

1、 Push pull structure ： Use two triodes or MOSFET, Exist in the circuit in push-pull mode . When the circuit is working , Two symmetrical switches have only one conduction at a time , So the conduction loss is small 、 Efficient . It can inject current into the load , You can also draw current from the load . The push-pull output stage improves the load capacity of the circuit , And increase the switching speed .

Above the picture is NPN T-triode , Here is PNP T-triode . There are two situations ：

Output high level ： Apply current to the load .

Output low level ： Pull the current from the load .

2、 Open drain structure （OD）： Compare push-pull structure , The open drain structure has only one triode or MOS tube .

It's called open leak , Because MOS The tube is divided into three poles ： Source pole 、 Grid 、 Drain electrode . Open drain output , So it's called open leak ; If it's a triode ： The base 、 Collector 、 The emitter , Open collector , So it is called open set output （OC）.

Open set output ,NPN triode ：

Vin High level , Triode conduction , External output low level , The outside is pulled directly down .

Vin Low level , Collector （C） Open the way , The output level state is determined externally .

The above analysis adopts triode ,MOS Tube similar .

therefore , Push pull structure can output high and low levels . Open drain output can only output low level , The high level is determined by the external circuit .

2、 Line and function

Line and ： all GPIO High output means high , As long as there is one output low , The whole line is low , This is it. “ And ” It means .

1、 Push pull structure , Two GPIO The port is connected to a line , Suppose the left PMOS Conduction , Dexter NMOS Conduction ,Vdd Will pass two MOS The pipe is directly grounded , because MOS The on resistance of the tube is not large , It will cause a large current , Directly damage these two GPIO mouth , therefore , Push pull output does not support line and .

note： In fact, it is not necessarily above NMOS below PMOS, As long as the upper and lower pipes are of different types , It can ensure that only one pipe is connected at the same time , You can output high and low levels respectively .

2、 Open drain structure ： If many GPIO It is an open drain structure , Got a line , Here's the picture . The output high level of the open drain structure is pulled up externally , If there is one GPIO Grounding , Then the current will flow into the ground through the pull-up resistor , Because there is a pull-up resistor , So the current is not big , No damage GPIO mouth .

Line and , yes I2C The basis of the agreement ！

Section

mode	open-drain	push-pull
speed	slower	fsater
power	higher	lower
slave clock stretching	yes	not supported

power Power consumption , Open the drain because of the pull-up resistance , Each high and low level conversion will consume energy , Therefore, the power consumption is high .

clock stretching Clock extension , Open drain supports clock extension , Push-pull structure does not support clock extension . The reason is the same as the push-pull line above . Some people will have questions , Clock extension is not in SCL When the electricity is low , Pull from the equipment SCL Line? ？ There should be no problem . But if it is push-pull GPIO, At this time, the master controller will try to raise SCL , Can find SCL Pulled down by the slave , At this time, there will be a short circuit .

Once again remind , Line and ： When only one device on the bus outputs low level , The whole bus is in the low-level state , At this time, the bus is called occupied state .

3、 Pull up resistance calculation

1、 The pull-up resistance is too small , High current , Port low level level increase , You will find that the level on the bus cannot be pulled 0V.

2、 Excessive pull-up resistance , The rising edge time increases , A square wave may become a triangular wave .

Therefore, it is very important to calculate an accurate pull-up resistance . Calculate the resistance of the pull-up resistance , There is a clear calculation formula ：

Maximum resistance And rising edge time tr 、 Bus capacitance Cb 、 Standard rising edge time 0.8473 of .

Minimum resistance And the power supply Vdd voltage 、GPIO Maximum output voltage Vol、 GPIO Maximum current Vol of .

check 《I2C-bus specification and user manual.pdf》7.1 section ：

check 《I2C-bus specification and user manual.pdf》 surface 10：

From the above figure, we can get the calculation formula of maximum resistance and minimum resistance and the following data ：

1、 The standard model ：0~100KHz, Rising edge time requirements tr = 1us

2、 Fast mode ：100~400KHz, Rising edge time requirements tr = 0.3us

3、 High speed mode ：up to 3.4MHz, Rising edge time requirements tr = 0.12us

note： The rising edge time tr yes 0.3Vdd To 0.7Vdd It's time to .

hypothesis ：Vdd yes 1.8V,Cb Bus capacitance 200pF（ Although the agreement stipulates the maximum load capacitance 400pF, Actually more than 200pF The waveform is very bad , We use 200pF To calculate , It is suggested to use 100pF Calculation ）

The standard model ：

Fast mode ：

High speed mode ：

Minimum resistance （Vdd The bigger it is , The greater the pull-up resistance ）：

Be careful , High speed mode , The power supply voltage is generally 1.8 V, Will not use 3.3V, Because if you use 3.3V You will find that the minimum resistance is greater than the maximum resistance .

Use appropriate power supply voltage and appropriate pull-up resistance , Will make you I2C Transmission signal optimization .

The resistors we use at different rates are generally the following ：1.5K、2.2K、4.7K.

Pull up resistance diagram

3、I2C Transfer

0、Definition of timing

Want to explore I2C agreement , We must deeply understand the definition of various times , The following for F/S-mode

1. Set up time (Tsu)： Before the rising edge of the clock comes , The time interval when the input data has arrived and is stable .

2. Retention time (Thd)： After the rising edge of the clock , The time interval for which the input data continues to remain stable .

identifier	Definition
tf	Signal falling time
tr	Signal rise time
tLOW	Signal low level time
tHIGH	Signal high level time
tHD;DAT	Data retention time
tSU;DAT	Data establishment time
tSP	Input the burr pulse width that the filter must suppress
tBUF	Idle time for start and stop conditions
tHD;STA	Repeat the holding time of the starting condition
tSU;STA	The establishment time of the repetition starting condition
tSU;STO	Stop condition establishment time

Sr Restart ,S start-up ,P stop it .

The above parameters are in spec There are strict regulations in , Look up table , commonly standard mode and Fast mode together ,Hs mode Separate columns , surface 4、 surface 5、 surface 6、 surface 7：

Master

1. Provide clock SCL

2. Start and stop data transmission

3. Addressing other devices

slave

1. Addressed by the master

1、 Data validity

stay SCL During high level ,SDA Must be stable , So in general ,SCL High level width is small ,SDA High level width , It's the same with oscilloscope .

2、 Start and stop conditions

Starting conditions ：SCL High voltage usually ,SDA From high to low .

Stop conditions ：SCL High voltage usually ,SDA From low to high .

note： because SCL and SDA Two wires have pull-up resistors , Therefore, when idle, the two wires are high . therefore ,START The condition must be that some line is pulled down ,spec The rule is SDA Lower the line is the starting condition . This is also the reason why the start condition and stop condition cannot be interchanged .（ As for why not SCL Lower the line is the starting condition , You will understand after you see ）

byte format

1. The transmission length must be one byte （8 bit）

2. The number of bytes per transmission is unlimited

3. The data must be in MSB Start transmission , That is, first transmit the highest bit

4. The slave can connect the clock line SCL Keep low , Force the host to wait .

stay ACK after , The slave device can be pulled down SCL Line for clock extension （ For example, the slave device needs to prepare data ）

note：SCL At high level ,SDA Start sampling ,SDA High is 1, Low is 0.SCL During low level ,SDA Transform data . Not in SCL Change data during high level , Otherwise, it will be considered Start and stop conditions .

3、ACK or NACK

After each transmission of a byte , The slave device needs to respond , Respond ACK perhaps NACK.

ACK ： In the transport 8 bit in the future , In the ninth bit ,SCL High level , If SDA Is a low level , Description responded ACK.

NACK： In the transport 8 bit in the future , In the ninth bit ,SCL High level , If SDA Is a high level , Description responded NACK.

spec Stipulate that the following five situations will occur NACK

1. The address sent by the host to the bus , But there is no matching slave , So there comes NACK

2. The slave is in busy state , appear NACK

3. During transmission , Get data or commands from the machine that it doesn't understand .

4. During transmission , The slave cannot receive any more data bytes .

5. When the master receiver must send the signal of the end of transmission to the slave transmitter , There will be NACK.

4、write data

The host writes data to the slave , The last byte at the end of communication , The normal slave will respond to one ACK , Tell the host that the last byte is written successfully , At this time, the host will generate STOP The signal .

If the slave responds to the last byte NACK , The host will also generate a STOP The signal , And at this time, the host will report a ACK error .

How to deal with it at the upper level , It's about the top , Chip design I2C The peripheral controller must generate a ACK error. If I use theta Linux operating system , You can configure the upper layer to ignore the last ACK error .

5、read data

The host reads data from the slave , After the last byte , The master will give the slave a NACK , Tell the slave to stop reading data , Then the host generates a STOP The signal . This is the only one in the normal transmission process NACK

6、 Composite format

Repeat the start signal Sr Before and after , Two slave address Can be different . in other words , One I2C The host may not generate STOP The signal , Directly generate a repeat start signal to access another slave .（ If I2C There are multiple hosts on the bus , There is no need to arbitrate again , Save time ）

in addition , stay Linux In the system , because i2c_msg Provisions of the structure , A single stroke I2C Maximum transmission 64KB, exceed 64KB I want to do it again STOP Signal or Repeat the start signal .

7、I2C Transfer Regulation

1. With START Conditions begin

2. With STOP The conditions are over

3. The first byte transmitted is 7bit Slave address + 1bit Read write bit

4. Devices on each bus will compare STRAT Behind the signal 7bit Whether the address matches your own address

5. Every byte(8 bits) There will be ACK perhaps NACK

6. stay START Signal or repeated START After the signal , The slave must reset its own bus logic

7. One START There is a STOP The signal , Is an illegal format

8. host master Can not produce STOP The signal , But directly produce a repeated START The signal + Another device address , Start accessing another device directly

8、10-bit addressing

10 The bit slave address is specified as follows , among 11110 by 10 Indication signal of bit address ,A9-A0 Express 10bits Address ：

The host writes data to the slave （ need 2 bytes）

The host reads data from the slave （ need 3 bytes）

9、 Example of oscillograph

1. The host writes data to the slave

Above picture , People will be in SDA There are three very fine burrs found on the line , Every time it appears in the slave response ACK in the future . This is because the slave is pulled down SDA Line response ACK after , The release of the SDA Line , Because there is a pull-up resistor ,SDA The line is pulled high , Then the host took over immediately SDA Line , hold SDA Line pull down . That is, the burr is due to slave and master Change hands caused by jet lag .

Because the burr appears in SCL During low level , and SCL During low level ,SDA It can transform data , So it won't be right I2C Communication has a negative impact , This burr generally needs no attention .

If the waveform is not beautiful , You can find the original chip factory , See if it can be adjusted master Wire controlled setup time and hold time , To reduce the amplitude of the burr .

1. The host reads data from the slave

10、 Add

I2C The slave device is not supported in SCL and SDA An interrupt is initiated on the bus , Inform the master device to read data . The slave device with interruption needs to be connected with an additional medium break line , Inform the master that the data is ready , Let the master initiate the operation of reading data .

This undoubtedly increases the complexity of the system , Take up too much pin foot .I3C There is no such problem ,I3C Allow slave devices to SCL and SDA Initiate an interrupt on , It's called “ In band interrupt ”,I3C The back can speak .

4、I2C Synchronization And Arbitration

Three concepts ： The clock extends 、 Sync 、 arbitration

1、Clock stretching The clock extends

1. The clock extends ： By way of SCL The line remains low to suspend transmission . stay SCL Before pulling up again , The transfer cannot proceed .

2. The slave will pass SCL Line pull down , Force the host to enter the waiting state .

3. The clock extension function is optional , Not necessary .

byte level

The clock extension causes more time to store the received byte or prepare another byte to be transmitted

bit level

Reduce the bus clock by extending the low-level cycle of each clock . The speed of any host is compatible with the internal running speed of the device .

stay Hs mode, Only use byte level, That is, only one byte can be transmitted （8bits） Pull back low SCL Extend the clock . stay Standard-mode and Fast-mode, You can byte level It's fine too bit level,bit level It means that even if you transmit 2 bits , The slave can also be pulled down SCL Line for clock extension , Temporarily pause transmission .

Popular explanation of clock extension

I2C The master device always controls the clock line SCL, Whether writing to or reading from the device . In general , If the operation object is EEPROM Or other simple equipment , It doesn't matter , however , If the slave device is a processor , After receiving the command from the host, you need to process some operations and then return the results to the host . At this time, it may be too late to deal with . What do I do ？ At this time , The slave device will actively control the clock line to pull it down ！ Release the clock line until the data is ready , Give control back to MASTER. This is also I2C In the communication system , The only time the slave can control the bus ！

The key is a lot I2C The host does not support clock stretching function , therefore , Cannot and with clock stretching Function of slave communication ！ therefore , Before you choose the host device , This must be noted , Otherwise, the whole design scheme may be scrapped , Great influence .

2、Synchronization And Arbitration

I2C It is a multi master-slave architecture , That is, multiple can be connected to a bus at the same time I2C Host and multiple I2C Slave .

However, if two or more hosts send start signals to the bus at the same time and start transmitting data , This creates a conflict . To resolve this conflict , The decision of arbitration , This is it. I2C Arbitration on the bus .

I2C The arbitration on the bus is divided into two parts ：SCL Line synchronization and SDA Arbitration of lines , There is no sequential relationship between these two parts , At the same time .

SCL Synchronization

All hosts are SCL Output your own clock online , Therefore, the synchronization process needs to define its own clock .

SCL Synchronization is due to the fact that the bus has lines “ And ” The logical function of , That is, as long as one node sends a low level , The bus shows low level . When all nodes send high level , The bus can show high level . It is because of the line “ And ” The principle of logical function , When multiple nodes send clock signals at the same time , The unified clock signal is displayed on the bus . This is it. SCL Synchronization principle of .

The synchronization process is shown in the following figure ：

host 1 produce CLK1, host 2 produce CLK2, Simultaneous direction SCL Output your own clock online , because CLK2 The low level of is longer , therefore SCL The level appearing on the line and CLK2 bring into correspondence with . So in the first cycle ,CLK1 Later, it entered the high-level waiting state . Back SCL The level above is in CLK2 Subject to .

SDA Arbitration

SDA Line arbitration is also based on the bus with line “ And ” The principle of logical function . The node is sending 1 After bit data , Compare whether the data presented on the bus is consistent with the data sent by yourself . yes , Continue to send ; otherwise , Exit competition .

SDA The arbitration of the line can guarantee I2C When multiple master nodes attempt to control the bus at the same time, the communication is normal and the data is not lost . The bus system allows only one master node to continue to occupy the bus through arbitration .

1. In arbitration SDA on , here SCL High level .

2. A The host transmits high level ,B The host transmits low level ,A Loss of arbitration .

3. The host that loses arbitration will generate clock pulses , Until the end of missing arbitrated bytes .

Arbitration process ：

DATA1 and DATA2 They are the data signals sent by the two hosts to the bus ,SDA Is the data signal presented on the bus ,SCL It is the clock signal presented on the bus .

host 1、2 Send the start signal at the same time , stay clock1 , Both hosts sent high-level signals . At this time, the signal on the bus is high , Both master nodes detect that the signal on the bus is the same as the signal sent by themselves , Continue sending data .

The first 2 Clock cycles ,2 Each master node sends a low-level signal , The signal presented on the bus is low , Continue sending data .

In the 3 Clock cycles , Master node 1 Send high level signal , And the master node 2 Send low level signal . According to the bus line “ And ” The logical function of , The signal on the bus is low , At this time, the master node 1 It is detected that the data on the bus is different from the data sent by yourself , Just disconnect the output stage of the data , Change to slave receiving status . So the master node 2 Won the bus , And the data is not lost , That is, the data of the bus and the master node 2 The data sent is the same , And the master node 1 Continue to receive data after turning to a slave node , Also did not lose SDA Online data . Therefore, the data was not lost during the arbitration .

5、I2C Hs-mode

HS mode Why explain it alone ？ Because there are many differences between high-speed mode and other modes .

1. The speed is as high as 3.4MHz.

2. It's using SDAH and SCLH The signal line , No SDA and SCL

Master device

1. SDAH/SCLH There is an open drain output buffer, SCLH There is a current source pull-up circuit , This current source circuit is shortened SCLH The rise time of the signal . At any time Hs Only the current source of one host is valid in this mode .

2. No arbitration and clock synchronization , To speed up bit processing capacity . The arbitration process is generally used in the front F/S The mode ends after transmitting the host code .

3. High level and low level are 1:2 The ratio of generates a serial clock signal . The time sequence requirements for establishing and maintaining time are relieved .

4. High speed data SDAH And high-speed serial clock SCLH The line passes through this bridge and F/S Mode device SDA and SCL Lines separate . To reduce the SDAH and SCLH The capacitive load of the line , Make the rise and fall time faster .

Slave device

1. Hs Mode from machine parts to F/S The only difference from machine parts is the speed at which they work .Hs The mode slave is SCLH and SDAH Output has open drain output buffer .SCLH The pull-down transistor with optional pins can be used for stretching SCLH Low level of signal , But only in Hs After the response bit of mode transmission .

2. Hs The output of the mode device can suppress burrs , and SDAH and SCLH The output has a Schmitt trigger

3. Hs Output buffer pairs of mode devices SDAH and SCLH The falling edge of the signal has a slope control function

4. Adjusted serial data SDA And serial clock SCL Timing of signals . It is not necessary to connect with other bus systems such as CBUS compatible , They cannot work at an increased bit rate .

5. If the power supply voltage of the fast mode device is turned off ,SDA and SCL Of I/O The pin must be suspended , Do not block the bus .

6. External pull-up devices connected to the bus must be adjusted to accommodate the fast mode I2C Shorter maximum allowable rise time of the bus . The maximum load is 200pF Bus of , The pull-up device of each bus can be a resistor ; For load at 200pF~400pF Bus between , The pull-up device can be a current source （ Maximum 3mA） Or a switched resistor circuit , Here's the picture ：

Only Hs The system physics of mode devices I2C Bus configuration

（ Optional ） Series resistor Rs Protect I2C Bus device I/O Free from high voltage spikes on the bus , And minimize ringing and interference .

Two devices in the lower right corner , Not just from the device , It can also be the main equipment . This device has a MCS Current source . If there are many devices on the bus , It will lead to large bus capacitance , Raising the bus voltage is equivalent to charging the capacitor , It takes time , This will cause the rising edge of the waveform to be too slow , Therefore, adding a current source can make the rising edge very fast .

1、data transfer format in Hs-mode

1. START condition (S)

2. 8-bit master code (0000 1XXX)

3. Not-acknowledge bit (A)

2、 stay Hs Enable the current source pull-up circuit in mode

3、 After the next repeated start condition , Still in Hs-mode

As can be seen from the figure above , In fast mode （FS mode） Send next Master code, Then switch to high-speed mode （HS mode）, Send slave address .

In the first phase FS mode When , Send host code （0x0000 1xxx）, Arbitration will take place at this time . therefore Hs mode Phase has no clock synchronization and arbitration .

In the middle HS mode After transmission , If it's a STOP The signal , Then immediately return to F/S mode, If it is Sr Repeat start i The signal , Still stay Hs mode（ There is a description in the lower right corner ）

The picture above shows Hs mode Complete communication waveform diagram . First send the host code in fast mode , There is no need to reply from the machine . Then switch to high-speed mode , Will send a reSTART, And then data transmission .

We need to pay attention to the following points ：

1. Upper right corner t1 To tH In time , The clock can be extended .

2. Hs mode in , Only in byte level Level to extend the clock , That's one byte Extend the clock after transmission .

3. Pay attention to the diagram in the lower left corner , If it is a straight up and down waveform , It is the pull-up of the host current source . If it is the rising edge of a gentle slope , The resistance pulls up .

Bloggers will I2C spec Summarize separately , mean , Whether you are a single-chip microcomputer platform , still FreeRTOS platform , still Linux platform ,I2C spec It's all the same , So it is summarized as an article for everyone to check .