[quick start of Digital IC Verification] 23. AHB sramc of SystemVerilog project practice (3) (basic points of AHB protocol)

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One 、 Description of content

• basic AHB The signal
• AHB transmission

Two 、AHB Detailed introduction

2.1、 A typical AMBA 2.0 System

2.2、AHB Bus interconnection

AHB From the figure above, we can see that there are three types of signals that need to be transmitted ：

• HADDR
  • Direction is Master To Slave
• HWDATA
  • Direction is Master To Slave
• HRDATA
  • Direction is Slave To Master

There are multiple on the bus Master and Slave, But there can only be one bus at a time Master visit Slave, So you need a Arbiter To the arbitration address （HADDR） And write data （HWDATA）. Specific means , In the above figure, it is through Arbiter Choose MUX Some input signal of , And then MUX The output signal of is sent to each Slave（ Embodiment of shared bus ）, each Slave Decode separately , After translation, it will be received . Every Slave The address space is unique in the system .

each Slave Reading data for （HRDATA） Signal input to MUX The input end of the , And then through Decoder Choose MUX Some input signal of , And then MUX The output signal of is sent to each Matser（ Embodiment of shared bus ）. This Decoder yes HADDR Over here , Will do decoding , Through decoding, you will know which command this command is slave Received , Similarly, I will choose which slave Returned data , Then return to master in .

2.3、AHB transmission

The figure above highlights AHB Transmission process ： First Master Send a request to the arbiter （ Not shown in the picture ）, The arbiter will be based on each Master Request to send the results , Choose the corresponding Master Address MUX And data MUX Input . Then send it to each Slave,Slave It will decode itself , Decide whether to accept ！

Allow a master device to control the bus meaning ： Running a command occupies the bus . for instance ：Master1 Run the read command to access Slave2, Have been arbitrated ,Slave2 After returning the response , This order is over . After that ,Arbiter Will release the bus , Go to arbitration for the next round . about Slave Speaking of , It will decode according to the address ！

pull up HREADY The signal , The meaning of bus transmission completion ：Slave When it's done , Back in Data There will be a handshake at the same time Ready return . On behalf of me, this visit has OK 了 , tell Master Your visit is over , In this way, you can reapply for the bus .

notes ： This picture is a surprise during the interview , When learning, you can first understand , What is more important is what will be introduced later AHB sequential . in addition ,AHB At present, the bus is very mature, and there are ready-made IP, Interviewers are usually not required to design , Verification is also very mature , So more focus on Slave The timing of the mouth ！

2.4、Dummy/Default Master

2.4.1、Dummy Master（ With a few ）

• Granted when all masters SPLIT
  • Dummy Master meaning Mute Master, That is, only when others Master When there is no response , It will respond . A design to prevent the bus from hanging Dummy Master.
• Generates IDLE cycles only
  • IDLE yes TRANS A type in , There will be BUSY/IDLE These States
• Typically Master #0
  • Usually Master0 As Dummy Master
• Granted when Locked master gets SOLIT response

（ I see... In the back AHB sequential , Look back at these , Because there are some signals involved , Such as ：Locked、IDLE…）

2.5、Default Slave

Our address space division , Space is very big , Every IP After taking up part of the space , There is still some space IP The amount of , This part of the space is called the default space . If there is no default space , Then order it , No response returned （ handshake mechanisms ）, The whole system will hang up .

2.6、AHB The signal

2.7、 basic AHB The signal

• HRESETn
  • Low efficiency
• HADDR[31:0]
  • 32 Bit system address bus
• HWDATA[31:0]
  • Write data bus , Write from master to slave （M → S）
• HRDATA[31:0]
  • Read the data bus , Read from the slave device to the master device （S → M）
• HTRANS
  • Indicate the current transmission status
    • NONSEQ（10）、SEQ（11）、IDLE（00）、BUSY（01）
    • NONSEQ（10）、SEQ（11） At present, there is no distinction in the industry , The handling method is the same ！
• HSIZE
  • Indicate the current transmission size
• HBURST
  • Point out the transmitted burst type
• HRESP
  • Bus transmission status from slave device to master device
    • OKAY、ERROR、RETRY（ Retransmission , Rarely used ）、SPLIT（ Separate , Rarely used ）
• HREADY（ Whether the returned data is valid ）
  • high ： The slave device indicates the end of the transmission
  • Low level ： The slave device needs to extend the transmission cycle

2.8、 basic AHB transmission

• Two phases
  • Address cycle , only one cycle（ The control signal and the address signal are in the same beat ）
  • Data cycle , from HREADY The signal determines how many cycle
• Assembly line delivery
  • First, the address cycle , And then there's the data cycle

2.8.1、 A simple transmission without waiting state

• At the first vertical black line ：Master release address and control
• The second vertical black line ：Slave sample the address and control
• The third vertical black line ：Master sample the data

Q： If slave No, ready？

• A：HREADY Low in this cycle ！

2.8.2、 A simple transmission that requires two waiting cycles

• after 3 pat HREADY Just high , Before data reading and data writing .

2.8.3、 Assembly line （Pipeline）

• Running water , That is, the address and data are sent at the same time .

2.8.3、Burst Transfer（ Basically useless , As an understanding, you can ！）

2.9、 Transfer type

• HTRANS[1:0]： Current transmission status
  • IDLE、BUSY、NONSEQ、SEQ（ The latter two are combined , Don't make a distinction ）
• 00：IDLE（ Use less ）
  • The master device occupies the bus , But no transmission
  • two burst There is no master device sending IDLE
• 01：BUSY（ Use less ）
  • The master device occupies the bus , But in burst During the transmission, it is not ready for the next transmission
  • successively burst Transmission intermediate main equipment sends BUSY
• 10：NOSEQ【single】
  • Indicates a single data transmission （single）
  • Or once burst The first data transmitted
  • The address and control signals are independent of the last transmission
• 11：SEQ【Burst】
  • indicate burst Transmit the next data
  • The address is related to the address of the last transmission

notes ： Direct judgment in actual use HTRANS The high , by 1 Indicates valid （ namely NOSEQ/SEQ Don't make a distinction ）. about slave Speaking of it, I don't do it SEQ and NOSEQ Distinguishing , Because we usually put ADDR coming , Not paying attention is single still burst！

notes ： Here is just a concept to remember , Another thing to know , Only Burst Only then SEQ,Single When I was young, it was just NOSEQ！

2.10、 Examples of transmission types

2.11、 other AHB Control signals

• HWRITE

  • High level （1）： Write
  • Low level （0）： read

• HSIZE[2:0]

  • 000：8bits 100：128bits
  • 001：16bits 101：126bits
  • 010：32bits 110：512bits
  • 011：64bits 111：1024bits
  • The maximum value is limited by the configuration of the bus
  • Usually use 32bits（010）

• HPORT[3:0]（ It's not very useful ）【 Understanding can 】

  • HPORT[0]：OPCODE/DATA（ Operands / data ）
  • HPORT[1]：USER/PRIVILGED（ Ordinary users / Privileged users ）
  • HPORT[2]：Bufferable/Non-Bufferable
  • HPORT[3]：Cacheable/Non-Cacheable

notes ：AHB Now it is mostly used for small MCU,HPORT Basically can't use ！

2.12、AHB Control signal summary

2.13、Review

Q： Where does the address of the address decoder come from ？

• A： The system address space division design stipulates , The space division of different projects is different ！ Every AHB Slave There is one. HSEL,HSEL At the same time, only one will be effective ！

Q：master One time 4 An address , It corresponds to different slave Do you ？

• A：4 One address corresponds to one slave, Four addresses are usually continuous .

Q：HSIZE Address or data transmission bit width ？

• A：HSIZE It refers to the effective transmission data bit width . The data transmission bit width is 32 position , adopt HSIZE It can be stipulated that 32 Bit inside is effective transmission 8/16 A still 32 position , No, 24 position .
• If effective 8 position , Specifically 4 individual 8 Which one of them 8 position , By address [1:0] decision . If the address [1:0]=0, Representing data [7:0] It works ; If the address [1:0]=1, Representing data [15:8] It works ; If the address [1:0]=2, Representing data [23:16] It works ; If the address [1:0]=3, Representing data [31:24] It works .

The fixed address bus is 32 position （32 System ）, Then the address space is equivalent to 4G.

Q：HBURST effect ？

• A： In practical engineering, this signal has little effect . It is stipulated in the agreement that ： The access address space between commands is continuous , You can calculate the address of the next command with the first command .
• eg：BURST 2 ;0x000C -> 0x000C 0x000D 0x000E 0x000F ; 0x0010 -> 0x0010 0x0011 0x0012 0x0013; effect ： I sent an order and the address is 0x000C, And tell the command is BURST 2, It means I will send it continuously 2 individual 32 Access to bit address space . because AHB Each command in the protocol brings the address , So do slave I usually don't look at it when I'm HBURST The signal .

Interview frequently asked ： Draw a picture AHB Timing signal ？ Name of main signal ？ Each signal acts ？