I2C bus timing explanation

1 I2C brief introduction

Bus （Bus） It is a common communication trunk line for transmitting information between various functional components of a computer . and I2C One of the biggest advantages of bus is , It only needs data （SDA） And the clock （SCL） Two buses can support the communication between master equipment and multiple slave equipment . chart 1 It shows the typical characteristics of embedded system I2C Bus . Microcontroller represents I2C Main controller , As the main equipment , And control each slave device , These slave devices include but are not limited to ,IO Extender , All kinds of sensors ,EEPROM,ADC/DAC wait . And all this is only by the main equipment 2 Two pins control .

                                                                      chart 1 A typical I2C Bus

2 I2C Electrical characteristics

I2C The bus consists of two bidirectional signal lines . One is a data line SDA, The other is the clock line SCL.I2C The design of open drain is adopted , It will only pull down the bus , or “ Release ” It and let the pull-up resistor pull it up . In idle state （ That is, when there is no data transmission on the bus ）, The two signal lines are at the high level at the same time after the pull-up resistor . chart 2 Shows the current flow when pulling down the bus . When you want to transmit Low-Level Logic , Meeting ** Pull down FET , This will result in a short circuit to bus ground , Realize the pull-down of the bus .

                                                        chart 2 Use the open drain interface to pull down the bus

When the slave device or master device wants to transmit logic high level , It simply releases the bus by turning off the pull down FET . The bus voltage can float up , And the pull-up resistor pulls up the bus voltage to the power supply voltage , This will be interpreted as high level . chart 3 Shows the current flow through the pull-up resistor . Closing the pull down FET is equivalent to opening it , Thus, the bus cannot be grounded , Realize the pull-up of the bus .

                                                          chart 3 Use the open drain interface to release the bus

3 I2C Interface

I2C The bus has standard bidirectional interface , The master device triggers the data transmission of the slave device , The slave device cannot actively transmit data .

3.1 START and STOP Conditions

When the master device wants to communicate with the slave device , The master device sends a message through the STAR or STOP Condition to start or stop data transmission . chart 4 Showing a START and STOP Examples of conditions , When SCL For high voltage ,SDA The transition from high to low on the line defines START Conditions . When SCL For high voltage ,SDA The transition from low to high on the line defines STOP Conditions .

                                                          chart 4 START and STOP Examples of conditions

3.2 Data validity and byte format

Pictured 5 Shown , When the master device sends START After the condition ,SCL During each clock pulse SDA Only one data bit can be transmitted , in other words SDA Transmitting a byte requires 8 individual SCL Clock cycle . This byte can be the device address , Register address , It can also be written from the device or read from the device . Data is transmitted first to the highest bit （MSB）. stay START and STOP Between conditions , Any number of data bytes can be transmitted from the master device to the slave device . Be careful ：SDA The data on the line must remain stable during the high level of the clock cycle , Because when SCL For high level, the change of data line is interpreted as control command （START or STOP）.

3.3 ACK and NACK

After each data byte or address byte is transmitted , There is also a message from the receiver ACK/NACK position .
When in ACK/NACK During the relevant clock cycle SDA Keep the line low , This is interpreted as ACK.ACK Bit indicates that byte data transmission is valid , You can send the next byte . Send... At the receiver ACK Before , The sender must release SDA Line . Enables the receiver to ACK/NACK During the low phase of the relevant clock cycle SDA Line .
When in ACK/NACK During the relevant clock cycle SDA Keep the line high , This is interpreted as NACK. There are several conditions that can lead to the generation of NACK：
• The communicating party cannot receive or send , Some functions are being performed in real time , And not ready to start communication with the master station .
• During transmission , The receiver gets data or commands it doesn't understand .
• During transmission , The receiver cannot receive any more data bytes .
• The main receiver reads the data and passes NACK Indicate to the slave .

                                                        chart 5 ACK、NACK And single byte data transmission example

4 I2C The data transfer

I2C Each slave device on the bus has its specific device address , So that the main equipment can I2C Multiple slave devices on the bus are managed . In order to realize the writing and reading of data from the master device to the slave device , The usual way is through registers in the slave device .
The register serves as the data storage unit of the slave device , Contains some specific information . The master device is ready to write configuration information , Or read data information , You must first write a specific instruction to the register of the slave device , To instruct the slave device to complete the corresponding task .

4.1 Write data to the slave device

Pictured 6 Shown , When the main equipment passes I2C When the bus writes data to the slave , The master device must first send the starting condition with the slave device address on the bus , And the last bit is set to 0（R/W position ）, This bit indicates write . After sending the reply bit from the device , The master device will send the register address of the register it wishes to write . The slave device will reconfirm , Let the master know it's ready . After that , The master device will start sending data to the registers of the slave device , Until the master device sends all the required data （ Sometimes it's just a byte ）, The main equipment will be in STOP Conditional termination of transmission . 

                                                        chart 6 An example of writing a single byte from a register

4.2 Read data from the device

Pictured 7 Shown , Reading from a slave device is very similar to writing , But it takes some extra steps . To read from the device , The master device must first indicate to the slave device which register it wants to read from . This is when the master device starts transmission in a similar way to writing , By sending R/W Bit is equal to 0（ Means write ） The address of , Then there is the register address you want to read from . Once the slave device confirms the register address , The master device will send... Again START Conditions , Then the slave device address ,R/W Bit is set to 1（ Means read ）. This time, , The slave device will acknowledge the read request , Master release SDA Bus , However, the clock will continue to be provided to the slave . During this part of the communication , The master device will become the master receiver , The slave device will become the slave transmitter .
The master will continue to send clock pulses , But will release SDA Line , So that the slave device can transmit data . At the end of each data byte , The master device will send... To the slave device ACK, Let the slave know that it is ready to receive more data . Once the master device receives the expected number of bytes , It will send a NACK, Send a signal to the slave device to stop communication and release the bus . Then the main device will be STOP Conditional end communication .

                                                        chart 7 An example of reading a single byte from a register