[Digital IC hand tearing code] Verilog edge detection circuit (rising edge, falling edge, double edge) | topic | principle | design | simulation

Preface

This series aims to provide 100% Accurate numbers IC Design / Verify the title of the hand tearing code link , principle ,RTL Design ,Testbench And reference simulation waveform , The content of each article is checked by simulation . The quick navigation links are as follows ：

Odd frequency division
Even frequency division
Semi integer batch
decimal / Fractional frequency division
Sequence detector
Mode three detector
Beverage machine
Asynchronous reset , Simultaneous release
Edge detection （ Rising edge , Falling edge , On both sides )
Full adder , Half adder
Gray code to binary
single bit Cross clock domain （ Two beats , Edge synchronization , Pulse synchronization ）
Sync FIFO

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Links are as follows
HDLBits — Verilog Practice

Edge detection circuit problem

1. Use Verilog Language , Design the rising edge detection circuit .
2. Use Verilog Language , Design the falling edge detection circuit .
3. Use Verilog Language , Design double edge detection circuit .

Principle of edge detection circuit

Here is to explain the principle , We need to analyze the characteristics of the edge circuit

For a rising edge circuit , If used clk Signals and registers are sampled , The previous shot was picked 0, The input result of the last beat is 1, Then through the operation of combinatorial logic , For the previous shot A Express , For the next shot B Express ,“!A & B” It is the rising edge detection we need .
Empathy , For the falling edge , The previous shot was taken 1, The input result of the last beat is 0,A&!B, It is the falling edge detection circuit we need .
For bilateral edges , The output is ** “!A & B + A&!B” **, namely A^B Exclusive or operation

The specific sequence diagram is as follows

RTL Design

module edge_detect(clk,rst_n,signal,up_edge,down_edge,both_edge);

input clk;
input signal;
input rst_n;
output up_edge;
output down_edge;
output both_edge;

reg signal_r;

[email protected](posedge clk or negedge rst_n)
begin
if(!rst_n)
signal_r <= 1'b0;
else
signal_r <= signal;
end

assign up_edge   = !signal_r & signal;
assign down_edge = signal_r & !signal;
assign both_edge = signal_r  ^  signal;

endmodule

Testbench Design

`timescale 1ns / 1ps
module edge_detect_tb () ;

reg clk;
reg rst_n;
reg signal;

wire up_edge;
wire down_edge;
wire both_edge;

edge_detect u1(.clk(clk),
.rst_n(rst_n),
.signal(signal),
.up_edge(up_edge),
.down_edge(down_edge),
.both_edge(both_edge));

always #5 clk = !clk;

initial
begin
clk = 0;
rst_n = 1;
signal = 0;
#10
rst_n = 0;
#23
rst_n = 1;
#16
signal = 1;
#50
signal = 0;
#40
$stop;
end

endmodule

Result analysis

As shown in the figure, the rising and falling edges , Electric circuit output Edge arrival detected , Displayed in three wire type output On , The circuit design meets the expectation .