Constants, variables, and operators of SystemVerilog usage

Two state 、 Four state variable ：

Verilog background :

Verilog There are two basic data types ： Variable （reg） And network cable （wire）, This is the data type of four states （0、1、X、Z）.

RTL The code uses variables （reg） To store the values of combinatorial logic and sequential logic , It can be ：

 Scalar ; for example ：reg flag_overflow
 vector ;  for example ：reg[7:0] bus_addr
 Signed number 32 Bit variable （integer）;
 An unsigned number 64 Bit variables （time）;
 Floating point numbers （real）;
 Variables can also be used to define a fixed size array ; for example ： reg 

That is, the storage of these variables is static , It means that all variables cannot use the stack to save parameters and current values during the whole simulation process .

Ethernet cable wire Used to connect two design modules , Such as gate level components or instantiated modules .

SystemVerilog Two states （1/0） data type :

SystemVerilog The two-state data type in reduces the use of memory and improves the efficiency of simulation .

（1） Basic data type . Basic data type , There is no difference between signed and unsigned .

  

 （2） Integer data type .

       

 Two state and signed data types ：

 Example ：

bit a;         // Two states , Shanbit 

bit[31:0] b32; // Two states ,32 Bit unsigned number 

int c32;       // Two states ,32 Bits have signed numbers 

byte d8;       // Two states ,8 Bits have signed numbers 

shortint e16;  // Two states ,16 Bits have signed numbers 

longint 1;     // Two states ,64 Bits have signed numbers 

 In the process of data arithmetic operation , You need to always pay attention to distinguishing between symbols （shortint、int、longint、byte、integer） And unsigned data types . These are all integer data types .

SystemVerilog Yes reg The data type of has been improved ,reg Can be consecutively assigned statements 、 Gate logic and module direct drive .

SystemVerilog Introduce a new four state data type logic, Can replace reg; But it cannot be used in the case of bidirectional bus and multi drive , Only network cable types can be used at this time (wire).

A signed 、 Unsigned variables ：

bit              // 1 Bit two state signed integer 
byte             // 8 Bit two state signed integers 
shortint         // 8 Bit two state signed integers 
int              // 16 Bit two state signed integers 
longint          // 32 Bit two state signed integers 
real             // 64 position   Double precision floating point 
shortreal        // 32 position   Single-precision floating-point 

//wire/reg/logic integer:32 Bits have signed numbers  time:64 Bit unsigned number  
wire [7:0] addr;    // 8 position    Four states 
reg  [31:0] data;   // 32 position   Four states 
logic [7:0] enable; // 8 position    Four states 
integer  a,b,c;     // 32 position   Four states    A signed 

//  Checking the four state values 
if ($isunknown(data) )
$display(“@%0t : 4-state value detected“,$time);

constant Variable ：

SV Medium logic Data types and Verilog Medium reg The type is the same , It can be used interchangeably , It's more compatible with wire type .

//  constant 
16'habcd  // 16 Bit binary bit width ,---- ---- ---- ----, Hexadecimal numbers are hexadecimal numbers abcd
//  Variable 
logic a;  // 1bit
logic [3:0]b;  // 4bit
logic [31:0][31:0]c;  // 32x32bit

// logic  Regardless of wire reg 
logic [31:0] a, b, c;
assign c = a & b;

Arithmetic shift left - Logic shift left 、 Arithmetic shift right 、 Logical shift right ：

Arithmetic shift left is the same as logical shift left, which is the right complement 0,
Logical shift right is simple , Just move the whole binary number to the right , Left complement 0 that will do ,
The sign bits of arithmetic shift right should be moved together , And put the sign bit on the left , That is, if the sign bit is 1 Make up for it 1 The sign bit is 0 Make up for it 0.

<<     Move left （ Logic shift left 、 Arithmetic shift left ）
>>     Logical shift right  // Move the whole thing to the right , Left complement 0
>>>   Arithmetic shift right

Operator ：

   

Extra knowledge ：

//  Module declaration 
module adder (
    input logic [3:0] a, b,
    output logic [3:0] c
);
    assign c = a + b;
endmodul

//  Modularization 
logic [3:0] b, c;
adder adder_inst0(.a(4'b0010), .*);   // .* Indicates the instantiation of all subsequent ports with the same name : amount to   adder adder_inst0(.a(4'b0010), .b(b), .c(c)); 

enum enumeration

enum Syntax is often used to encode （ Including the coding of state machine ）.enum Variable of type , stay Vivado Enumeration items will be displayed in the simulation . Enumeration items are treated as constants , Enumeration item names of various enumeration types cannot conflict .enum Variable of type , Only enumeration items can be used in assignment .

grammar :

typedef enum <datatype> { // enum The body is often   Constant 
    IDEN_1, IDEN_2
} typename;

//  Definition 1
typedef enum logic [3:0] {  // [3:0] You can have more , No less 
    ALU_ADD, ALU_AND, ALU_SUB
} alufunc_t;

//  Use 
alufunc_t alufunc;   //  Variable name 

//  Definition 2
enum logic [3:0] {
    ALU_ADD, ALU_AND, ALU_SUB
} alufunc_without_typedef;

//  Definition 
typedef enum logic [1:0] {
    STATE_0, STATE_1, STATE_2
} state_t;

//  Use 
state_t  state, state_nxt;   //  Variable name 

always_ff @(posedge clk) begin
    if (~resetn) begin
        state <= state_t'(0);  // state <= '0  error , Cast type to required state_t type 
    end else begin
        state <= state_nxt;
    end
end

  Cast new type '( Old type concrete variable )