当前位置:网站首页>Always of SystemVerilog usage_ comb 、always_ iff
Always of SystemVerilog usage_ comb 、always_ iff
2022-07-06 14:21:00 【Then the dish】
always_comb
always_comb Each internal statement is a blocking assignment statement . Circuit statements... Cannot appear (assign)
always_comb It has the following properties :
Internal coverage
External atomicity
always_comb begin
a = 1'b1;
b = a;
a =1'b0;
c = a;
end
// Circuit input :1'b1;1'b0; // On the right (1'b1;1'b0; a) Remove the left side (a,b,c)
// Circuit output :(a,b,c)// On the left
// Running results a=1'b0, b=1'b1, c=1'b0,
assign a = b;
always_comb begin
b = 1'b1;
c = a;
b = 1'b0;
end
// First always_comb have to : c = a, b = 1'b0; Again assign have to :a = b = 1'b0; c = a = 1'b0
// therefore a=1'b0, b=1'b0, c=1'b0,
assign a = b;
always_comb begin
b = 1'b1;
c = b;
b = 1'b0;
end
// First always_comb have to : c = b = 1'b1; b = 1'b0 Again assign have to :a = b = 1'b0;
// therefore a=1'b0, b=1'b0, c=1'b1,
always_comb case
unique case
case There is no priority in the block , Parallel comparison .
// unique case
always_comb begin
b = 1'b0;
unique case (a[3:0])
4'd1: begin b = 1'b1; end
4'd0: begin b = 1'b0; end
default: begin end
endcase
end
priority case
case There is priority in the block , Serial comparison ( Compare in turn )
always_comb begin
priority case (1'b1)
a[3]: begin end
a[2]: begin end
default: begin end
endcase
end
// amount to :
/*
always_comb begin
if(a[3]) begin
end else if(a[2]) begin
end else if() begin end
end
*/
always_comb if and for
if
if and else Used for conditional judgment
always_comb begin
b = 1'b0;
if (a[3]) begin b = 1'b1; end
else if (a[2]) begin b = 1'b0; end
else begin end
end
for
for stay always_comb in , Will be interpreted as loop expansion .
logic [15:0]a;
logic [3:0] b;
always_comb begin
b = '0;
for (int i = 15; i >= 0; i--) begin
if (a[i]) begin
b = i[3:0];
break;
end
end
end
always_comb begin
for (int i = 0 ; i < 16; i ++) begin
if (i >= n) break;
end
end
always_comb begin
for (int i = 0; i < 16; i++) begin
a[i] = b[i] & (c[i] == d[i] | e[i]); // The compiler doesn't think i Is constant ,a[i:i+3] illegal
end
end
for (genvar i = 0; i < 16; i++) begin // genvar assign
assign a[i] = b[i] & (c[i] == d[i] | e[i]); // The compiler thinks i Is constant ,a[i:i+3] legal
always_comb begin
end
end
always_ff
always_ff Used to describe triggers .
always_ff @(posedge clk) begin
if (~resetn) begin
q <= '0; // Trigger non blocking assignment
end else if (en) begin
q <= d;
end
end
logic [3:0] a, a_nxt;
// always_ff Write only the trigger part Nonblocking assignment
always_ff @(posedge clk) begin
if (~resetn) begin
a <= '0;
end else if (en) begin
{a, b} <= {a_nxt, b_nxt};
end
end
always_comb begin
a_nxt = a;
// Logic that does not belong to a trigger , Written in always_comb Block assignment
unique case(a)
4'd3: begin
a_nxt = 4'd2;
end
default: begin
end
endcase
end
Thank you for sharing !!
(4 Bar message ) System Verilog grammar _ Record on pit -CSDN Blog
边栏推荐
- Experiment 8 exception handling
- Record once, modify password logic vulnerability actual combat
- Feature extraction and detection 14 plane object recognition
- HackMyvm靶机系列(6)-videoclub
- JDBC transactions, batch processing, and connection pooling (super detailed)
- Interpretation of iterator related "itertools" module usage
- 【数据库 三大范式】一看就懂
- JDBC事务、批处理以及连接池(超详细)
- 7-9 make house number 3.0 (PTA program design)
- Wei Shen of Peking University revealed the current situation: his class is not very good, and there are only 5 or 6 middle-term students left after leaving class
猜你喜欢
随机推荐
[data processing of numpy and pytoch]
Intranet information collection of Intranet penetration (4)
Get started with typescript
Hackmyvm target series (4) -vulny
Detailed explanation of network foundation routing
WEB漏洞-文件操作之文件包含漏洞
SQL注入
实验六 继承和多态
This article explains in detail how mockmvc is used in practical work
实验七 常用类的使用
[MySQL database learning]
HackMyvm靶机系列(2)-warrior
Feature extraction and detection 14 plane object recognition
实验五 类和对象
Intranet information collection of Intranet penetration (2)
小程序web抓包-fiddler
Ucos-iii learning records (11) - task management
Network layer - simple ARP disconnection
内网渗透之内网信息收集(五)
[insert, modify and delete data in the headsong educator data table]